diff options
| author | Bryan Wu <pengw@nvidia.com> | 2014-06-24 11:45:29 +0900 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-08-18 16:57:02 -0700 |
| commit | df3443dfa449ad02bef8ddf6e2c90a6fd9394fc9 (patch) | |
| tree | 208df055da17bf359f611abf18def134fb2c9a7b /arch/arm/cpu | |
| parent | 1899fac925eda817e12234aef3d01d354788662e (diff) | |
| download | blackbird-obmc-uboot-df3443dfa449ad02bef8ddf6e2c90a6fd9394fc9.tar.gz blackbird-obmc-uboot-df3443dfa449ad02bef8ddf6e2c90a6fd9394fc9.zip | |
ARM: tegra: Disable VPR
On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed. For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed).
This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/tegra-common/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra-common/ap.c | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra-common/vpr.c | 35 |
3 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index 892556e644..a18c318739 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -14,3 +14,4 @@ obj-y += clock.o obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o +obj-$(CONFIG_TEGRA124) += vpr.o diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 91d70da656..a17dfd1e22 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -163,4 +163,7 @@ void s_init(void) /* init the cache */ config_cache(); + + /* init vpr */ + config_vpr(); } diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c new file mode 100644 index 0000000000..f695811c9b --- /dev/null +++ b/arch/arm/cpu/tegra-common/vpr.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Tegra vpr routines */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra.h> +#include <asm/arch/mc.h> + +/* Configures VPR. Right now, all we do is turn it off. */ +void config_vpr(void) +{ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + + /* Turn VPR off */ + writel(0, &mc->mc_video_protect_size_mb); + writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED, + &mc->mc_video_protect_reg_ctrl); + /* read back to ensure the write went through */ + readl(&mc->mc_video_protect_reg_ctrl); +} |
