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authorTom Rini <trini@konsulko.com>2016-04-13 07:19:50 -0400
committerTom Rini <trini@konsulko.com>2016-04-13 07:19:50 -0400
commit814013253fd4cf932d0fb32f7043f09a2a748d9a (patch)
tree9d9f84d8b469beb5e8aade98c503db4ce51bb8d8 /arch/arm/cpu
parent39fbd987164336adc2ff7e5ab7a4268b8dcdee92 (diff)
parent59c9e9b408014025cfa158a98aeafbcf33aa2d3d (diff)
downloadblackbird-obmc-uboot-814013253fd4cf932d0fb32f7043f09a2a748d9a.tar.gz
blackbird-obmc-uboot-814013253fd4cf932d0fb32f7043f09a2a748d9a.zip
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm926ejs/mx27/reset.c8
-rw-r--r--arch/arm/cpu/armv7/mx6/Kconfig23
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c1
-rw-r--r--arch/arm/cpu/armv7/mx6/ddr.c44
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c36
-rw-r--r--arch/arm/cpu/armv7/mx7/Kconfig8
-rw-r--r--arch/arm/cpu/armv7/mx7/soc.c18
7 files changed, 93 insertions, 45 deletions
diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c
index f7b4a1c83e..e764986737 100644
--- a/arch/arm/cpu/arm926ejs/mx27/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx27/reset.c
@@ -27,14 +27,14 @@ void reset_cpu(ulong ignored)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
- writel(0x00000000, &regs->wcr);
+ writew(0x0000, &regs->wcr);
/* Write Service Sequence */
- writel(0x00005555, &regs->wsr);
- writel(0x0000AAAA, &regs->wsr);
+ writew(0x5555, &regs->wsr);
+ writew(0xAAAA, &regs->wsr);
/* Enable watchdog */
- writel(WCR_WDE, &regs->wcr);
+ writew(WCR_WDE, &regs->wcr);
while (1);
/*NOTREACHED*/
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index c72a150875..1bcd399093 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -60,6 +60,18 @@ config TARGET_CM_FX6
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
+config TARGET_GE_B450V3
+ bool "General Electric B450v3"
+ select MX6Q
+
+config TARGET_GE_B650V3
+ bool "General Electric B650v3"
+ select MX6Q
+
+config TARGET_GE_B850V3
+ bool "General Electric B850v3"
+ select MX6Q
+
config TARGET_GW_VENTANA
bool "gw_ventana"
select SUPPORT_SPL
@@ -92,12 +104,14 @@ config TARGET_MX6SLEVK
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
+ select MX6SX
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
+ select MX6SX
select DM
select DM_THERMAL
@@ -153,16 +167,25 @@ config TARGET_WANDBOARD
config TARGET_WARP
bool "WaRP"
+config TARGET_XPRESS
+ bool "CCV xPress"
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
default "mx6"
+source "board/ge/bx50v3/Kconfig"
source "board/aristainetos/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
+source "board/ccv/xpress/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/embest/mx6boards/Kconfig"
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 88380a6cd9..3b53842e40 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1183,6 +1183,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("PLL_NET %8d MHz\n", freq / 1000000);
printf("\n");
+ printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
#ifdef CONFIG_MXC_SPI
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index e457febf67..1e7ae28933 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -12,40 +12,20 @@
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/types.h>
+#include <wait_bit.h>
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-static int wait_for_bit(void *reg, const uint32_t mask, bool set)
-{
- unsigned int timeout = 1000;
- u32 val;
-
- while (--timeout) {
- val = readl(reg);
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- udelay(1);
- }
-
- printf("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- __func__, reg, mask, set);
- hang(); /* DRAM couldn't be calibrated, game over :-( */
-}
-
static void reset_read_data_fifos(void)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
/* Reset data FIFOs twice. */
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
}
static void precharge_all(const bool cs0_enable, const bool cs1_enable)
@@ -60,12 +40,12 @@ static void precharge_all(const bool cs0_enable, const bool cs1_enable)
*/
if (cs0_enable) { /* CS0 */
writel(0x04008050, &mmdc0->mdscr);
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
if (cs1_enable) { /* CS1 */
writel(0x04008058, &mmdc0->mdscr);
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
}
@@ -164,7 +144,7 @@ int mmdc_do_write_level_calibration(void)
* 7. Upon completion of this process the MMDC de-asserts
* the MPWLGCR[HW_WL_EN]
*/
- wait_for_bit(&mmdc0->mpwlgcr, 1 << 0, 0);
+ wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
/*
* 8. check for any errors: check both PHYs for x64 configuration,
@@ -289,7 +269,7 @@ int mmdc_do_dqs_calibration(void)
writel(0x00008028, &mmdc0->mdscr);
/* poll to make sure the con_ack bit was asserted */
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
/*
* Check MDMISC register CALIB_PER_CS to see which CS calibration
@@ -327,7 +307,7 @@ int mmdc_do_dqs_calibration(void)
* this bit until it clears to indicate completion of the write access.
*/
setbits_le32(&mmdc0->mpswdar0, 1);
- wait_for_bit(&mmdc0->mpswdar0, 1 << 0, 0);
+ wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
/* Set the RD_DL_ABS# bits to their default values
* (will be calibrated later in the read delay-line calibration).
@@ -372,7 +352,7 @@ int mmdc_do_dqs_calibration(void)
setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
/* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
- wait_for_bit(&mmdc0->mpdgctrl0, 1 << 28, 0);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
/*
* Check to see if any errors were encountered during calibration
@@ -431,7 +411,7 @@ int mmdc_do_dqs_calibration(void)
* setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
* no error bits were set.
*/
- wait_for_bit(&mmdc0->mprddlhwctl, 1 << 4, 0);
+ wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
/* check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
@@ -484,7 +464,7 @@ int mmdc_do_dqs_calibration(void)
* by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
* Also, ensure that no error bits were set.
*/
- wait_for_bit(&mmdc0->mpwrdlhwctl, 1 << 4, 0);
+ wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
/* Check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
@@ -532,7 +512,7 @@ int mmdc_do_dqs_calibration(void)
writel(0x0, &mmdc0->mdscr); /* CS0 */
/* Poll to make sure the con_ack bit is clear */
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 0);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
/*
* Print out the registers that were updated as a result
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 91a3debe91..d4b22ad7f3 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+ reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+ else
+ reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
writel(reg, &mxc_ccm->ccdr);
}
@@ -325,15 +328,30 @@ int arch_cpu_init(void)
*/
init_bandgap();
- /*
- * When low freq boot is enabled, ROM will not set AHB
- * freq, so we need to ensure AHB freq is 132MHz in such
- * scenario.
- */
- if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
- set_ahb_rate(132000000);
+ if (!IS_ENABLED(CONFIG_MX6UL)) {
+ /*
+ * When low freq boot is enabled, ROM will not set AHB
+ * freq, so we need to ensure AHB freq is 132MHz in such
+ * scenario.
+ *
+ * To i.MX6UL, when power up, default ARM core and
+ * AHB rate is 396M and 132M.
+ */
+ if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+ set_ahb_rate(132000000);
+ }
+
+ if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
+ /*
+ * According to the design team's requirement on i.MX6UL,
+ * the PMIC_STBY_REQ PAD should be configured as open
+ * drain 100K (0x0000b8a0).
+ * Only exists on TO1.0
+ */
+ writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
+ }
- /* Set perclk to source from OSC 24MHz */
+ /* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
set_preclk_from_osc();
#endif
diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index 97d62389fd..ecfa4a2c35 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -15,6 +15,13 @@ choice
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
+ select MX7D
+ select DM
+ select DM_THERMAL
+
+config TARGET_WARP7
+ bool "warp7"
+ select MX7D
select DM
select DM_THERMAL
@@ -24,5 +31,6 @@ config SYS_SOC
default "mx7"
source "board/freescale/mx7dsabresd/Kconfig"
+source "board/warp7/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index ba6cfb9dce..073bbc6d01 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -165,6 +165,21 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
return val;
}
+static bool is_mx7d(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ int val;
+
+ val = readl(&fuse->tester4);
+ if (val & 1)
+ return false;
+ else
+ return true;
+}
+
u32 get_cpu_rev(void)
{
struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
@@ -172,6 +187,9 @@ u32 get_cpu_rev(void)
u32 reg = readl(&ccm_anatop->digprog);
u32 type = (reg >> 16) & 0xff;
+ if (!is_mx7d())
+ type = MXC_CPU_MX7S;
+
reg &= 0xff;
return (type << 12) | reg;
}
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