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| author | Mingkai Hu <mingkai.hu@nxp.com> | 2016-02-02 11:28:03 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-02-24 08:40:56 -0800 |
| commit | bbc8e053bad16366fc74943ce4c69a910c31b8b8 (patch) | |
| tree | 16ceab0d9a3f04295a2d9bdffbf0424d5cb99f36 /arch/arm/cpu/armv8/fsl-layerscape/soc.c | |
| parent | 3e0a0fbbac48e47d45e234691fddb55194052bed (diff) | |
| download | blackbird-obmc-uboot-bbc8e053bad16366fc74943ce4c69a910c31b8b8.tar.gz blackbird-obmc-uboot-bbc8e053bad16366fc74943ce4c69a910c31b8b8.zip | |
armv8/ls1043a: Implement workaround for erratum A009660
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7ff01481be..213ce3a824 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -213,6 +213,24 @@ static void erratum_a009929(void) #endif } +/* + * This erratum requires setting a value to eddrtqcr1 to optimal + * the DDR performance. The eddrtqcr1 register is in SCFG space + * of LS1043A and the offset is 0x157_020c. + */ +#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ + && defined(CONFIG_SYS_FSL_ERRATUM_A008514) +#error A009660 and A008514 can not be both enabled. +#endif + +static void erratum_a009660(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009660 + u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; + out_be32(eddrtqcr1, 0x63b20042); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void) /* Erratum */ erratum_a009929(); + erratum_a009660(); } #endif |
