armv8/fsl_lsch3: Change arch to fsl-layerscape

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

1 files changed, 86 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
new file mode 100644
index 0000000000..73e48a7d58
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ifc.h>
+#include <asm/arch/soc.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_LS2085A
+static void erratum_a008751(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+	writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
+#endif
+}
+
+static void erratum_rcw_src(void)
+{
+#if defined(CONFIG_SPL)
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+	u32 val;
+
+	val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+	val &= ~DCFG_PORSR1_RCW_SRC;
+	val |= DCFG_PORSR1_RCW_SRC_NOR;
+	out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
+#endif
+}
+
+#define I2C_DEBUG_REG 0x6
+#define I2C_GLITCH_EN 0x8
+/*
+ * This erratum requires setting glitch_en bit to enable
+ * digital glitch filter to improve clock stability.
+ */
+static void erratum_a009203(void)
+{
+	u8 __iomem *ptr;
+#ifdef CONFIG_SYS_I2C
+#ifdef I2C1_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C2_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C3_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C4_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#endif
+}
+
+void fsl_lsch3_early_init_f(void)
+{
+	erratum_a008751();
+	erratum_rcw_src();
+	init_early_memctl_regs();	/* tighten IFC timing */
+	erratum_a009203();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	return 0;
+}
+#endif