Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
	boards.cfg

31 files changed, 739 insertions, 328 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 28c16f8d02..828d10bb5a 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -144,6 +144,19 @@ int arch_misc_init(void)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*
+ * In the case of non-SPL based booting we'll want to call these
+ * functions a tiny bit later as it will require gd to be set and cleared
+ * and that's not true in s_init in this case so we cannot do it there.
+ */
+int board_early_init_f(void)
+{
+	prcm_init();
+	set_mux_conf_regs();
+
+	return 0;
+}
+
+/*
  * This function is the place to do per-board things such as ramp up the
  * MPU clock frequency.
  */
@@ -224,7 +237,7 @@ void s_init(void)
 	set_uart_mux_conf();
 	setup_clocks_for_console();
 	uart_soft_reset();
-#ifdef CONFIG_NOR_BOOT
+#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();
 	gd->have_console = 1;
@@ -232,20 +245,13 @@ void s_init(void)
 	gd = &gdata;
 	preloader_console_init();
 #endif
-	prcm_init();
-	set_mux_conf_regs();
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
 #endif
+#ifdef CONFIG_SPL_BUILD
+	board_early_init_f();
 	sdram_init();
-}
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
 }
-#endif /* !CONFIG_SYS_DCACHE_OFF */
+#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 0672798fe0..ec7d46838b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -170,8 +170,19 @@ void do_enable_clocks(u32 *const *clk_domains,
 	};
 }
 
+/*
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first.  This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
+ */
+__weak void scale_vcores(void)
+{
+}
+
 void prcm_init()
 {
 	enable_basic_clocks();
+	scale_vcores();
 	setup_dplls();
 }
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index d0bc2340c8..31188c85bc 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
 
 void setup_clocks_for_console(void)
 {
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
 	/* Do not add any spl_debug prints in this function */
 	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
 			MODULE_CLKCTRL_MODULEMODE_MASK,
 			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		clkctrl = readl(&cmwkup->wkup_uart0ctrl);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+	}
 }
 
 void enable_basic_clocks(void)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 9a625c4661..fc66872a31 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -94,7 +94,20 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 	writel(regs->emif_rd_wr_exec_thresh,
 	       &emif_reg[nr]->emif_rd_wr_exec_thresh);
 
+	/*
+	 * for most SOCs these registers won't need to be changed so only
+	 * write to these registers if someone explicitly has set the
+	 * register's value.
+	 */
+	if(regs->emif_cos_config) {
+		writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+		writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+		writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+	}
+
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 2c67c322ca..8b7527c5b4 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -21,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	sdram_init();
+#endif
+
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
 			(void *)CONFIG_SYS_SDRAM_BASE,
@@ -111,7 +115,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 #endif
 #ifdef CONFIG_AM43XX
 	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
-	while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+	while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
 		;
 	writel(0x80000000, &ddrctrl->ddrioctrl);
 
diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk
new file mode 100644
index 0000000000..09eab70955
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/config.mk
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= boot.bin
+else
+ALL-y	+= u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
index 2fbf60d542..8d86f97e3d 100644
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ b/arch/arm/cpu/armv7/at91/cpu.c
@@ -61,6 +61,8 @@ int print_cpuinfo(void)
 
 void enable_caches(void)
 {
+	icache_enable();
+	dcache_enable();
 }
 
 unsigned int get_chip_id(void)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index bc5fc423d6..a2c4032fed 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -354,41 +354,10 @@ void invalidate_icache_all(void)
 }
 #endif
 
-/*
- * Stub implementations for outer cache operations
- */
-void __v7_outer_cache_enable(void)
-{
-}
-void v7_outer_cache_enable(void)
-	__attribute__((weak, alias("__v7_outer_cache_enable")));
-
-void __v7_outer_cache_disable(void)
-{
-}
-void v7_outer_cache_disable(void)
-	__attribute__((weak, alias("__v7_outer_cache_disable")));
-
-void __v7_outer_cache_flush_all(void)
-{
-}
-void v7_outer_cache_flush_all(void)
-	__attribute__((weak, alias("__v7_outer_cache_flush_all")));
-
-void __v7_outer_cache_inval_all(void)
-{
-}
-void v7_outer_cache_inval_all(void)
-	__attribute__((weak, alias("__v7_outer_cache_inval_all")));
-
-void __v7_outer_cache_flush_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_flush_range(u32 start, u32 end)
-	__attribute__((weak, alias("__v7_outer_cache_flush_range")));
-
-void __v7_outer_cache_inval_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_inval_range(u32 start, u32 end)
-	__attribute__((weak, alias("__v7_outer_cache_inval_range")));
+/*  Stub implementations for outer cache operations */
+__weak void v7_outer_cache_enable(void) {}
+__weak void v7_outer_cache_disable(void) {}
+__weak void v7_outer_cache_flush_all(void) {}
+__weak void v7_outer_cache_inval_all(void) {}
+__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
+__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 1fea4d6663..400d134d54 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
 	struct exynos4_clock *clk =
 		(struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int addr;
+	unsigned int addr, clear_bit, set_bit;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -877,44 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 	 * CLK_DIV_FSYS2
 	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
 	 * CLK_DIV_FSYS3
-	 * MMC4_PRE_RATIO [15:8]
+	 * MMC4_RATIO [3:0]
 	 */
 	if (dev_index < 2) {
 		addr = (unsigned int)&clk->div_fsys1;
-	}  else if (dev_index == 4) {
+		clear_bit = MASK_PRE_RATIO(dev_index);
+		set_bit = SET_PRE_RATIO(dev_index, div);
+	} else if (dev_index == 4) {
 		addr = (unsigned int)&clk->div_fsys3;
 		dev_index -= 4;
+		/* MMC4 is controlled with the MMC4_RATIO value */
+		clear_bit = MASK_RATIO(dev_index);
+		set_bit = SET_RATIO(dev_index, div);
 	} else {
 		addr = (unsigned int)&clk->div_fsys2;
 		dev_index -= 2;
+		clear_bit = MASK_PRE_RATIO(dev_index);
+		set_bit = SET_PRE_RATIO(dev_index, div);
 	}
 
-	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
-			(div & 0xff) << ((dev_index << 4) + 8));
-}
-
-/* exynos4x12: set the mmc clock */
-static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
-{
-	struct exynos4x12_clock *clk =
-		(struct exynos4x12_clock *)samsung_get_base_clock();
-	unsigned int addr;
-
-	/*
-	 * CLK_DIV_FSYS1
-	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
-	 * CLK_DIV_FSYS2
-	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
-	 */
-	if (dev_index < 2) {
-		addr = (unsigned int)&clk->div_fsys1;
-	} else {
-		addr = (unsigned int)&clk->div_fsys2;
-		dev_index -= 2;
-	}
-
-	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
-			(div & 0xff) << ((dev_index << 4) + 8));
+	clrsetbits_le32(addr, clear_bit, set_bit);
 }
 
 /* exynos5: set the mmc clock */
@@ -1612,10 +1594,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
 		else
 			exynos5_set_mmc_clk(dev_index, div);
 	} else {
-		if (proid_is_exynos4412())
-			exynos4x12_set_mmc_clk(dev_index, div);
-		else
-			exynos4_set_mmc_clk(dev_index, div);
+		exynos4_set_mmc_clk(dev_index, div);
 	}
 }
 
diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c
index cca925e42c..9b6ee69f46 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -162,7 +162,7 @@ void mem_ctrl_init(int reset)
 
 	/* If there are any other memory variant, add their init call below */
 	if (param->mem_type == DDR_MODE_DDR3) {
-		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
+		ret = ddr3_mem_ctrl_init(mem, reset);
 		if (ret) {
 			/* will hang if failed to init memory control */
 			while (1)
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 487e6f423f..b86dd2d650 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -6,6 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
 #include <config.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -16,7 +17,11 @@
 #include "exynos5_setup.h"
 #include "clock_init.h"
 
-#define TIMEOUT	10000
+#define TIMEOUT_US		10000
+#define NUM_BYTE_LANES		4
+#define DEFAULT_DQS		8
+#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
 
 #ifdef CONFIG_EXYNOS5250
 static void reset_phy_ctrl(void)
@@ -28,8 +33,7 @@ static void reset_phy_ctrl(void)
 	writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-		       int reset)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 {
 	unsigned int val;
 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
@@ -177,7 +181,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(val, &phy1_ctrl->phy_con1);
 
 		writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
-		i = TIMEOUT;
+		i = TIMEOUT_US;
 		while ((readl(&dmc->phystatus) &
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
@@ -221,8 +225,220 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 #endif
 
 #ifdef CONFIG_EXYNOS5420
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-		       int reset)
+/**
+ * RAM address to use in the test.
+ *
+ * We'll use 4 words at this address and 4 at this address + 0x80 (Ares
+ * interleaves channels every 128 bytes).  This will allow us to evaluate all of
+ * the chips in a 1 chip per channel (2GB) system and half the chips in a 2
+ * chip per channel (4GB) system.  We can't test the 2nd chip since we need to
+ * do tests before the 2nd chip is enabled.  Looking at the 2nd chip isn't
+ * critical because the 1st and 2nd chip have very similar timings (they'd
+ * better have similar timings, since there's only a single adjustment that is
+ * shared by both chips).
+ */
+const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+
+/* Test pattern with which RAM will be tested */
+static const unsigned int test_pattern[] = {
+	0x5a5a5a5a,
+	0xa5a5a5a5,
+	0xf0f0f0f0,
+	0x0f0f0f0f,
+};
+
+/**
+ * This function is a test vector for sw read leveling,
+ * it compares the read data with the written data.
+ *
+ * @param ch			DMC channel number
+ * @param byte_lane		which DQS byte offset,
+ *				possible values are 0,1,2,3
+ * @return			TRUE if memory was good, FALSE if not.
+ */
+static bool dmc_valid_window_test_vector(int ch, int byte_lane)
+{
+	unsigned int read_data;
+	unsigned int mask;
+	int i;
+
+	mask = 0xFF << (8 * byte_lane);
+
+	for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
+		read_data = readl(test_addr + i * 4 + ch * 0x80);
+		if ((read_data & mask) != (test_pattern[i] & mask))
+			return false;
+	}
+
+	return true;
+}
+
+/**
+ * This function returns current read offset value.
+ *
+ * @param phy_ctrl	pointer to the current phy controller
+ */
+static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
+					       *phy_ctrl)
+{
+	return readl(&phy_ctrl->phy_con4);
+}
+
+/**
+ * This function performs resync, so that slave DLL is updated.
+ *
+ * @param phy_ctrl	pointer to the current phy controller
+ */
+static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
+{
+	setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
+	clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
+}
+
+/**
+ * This function sets read offset value register with 'offset'.
+ *
+ * ...we also call call ddr_phy_set_do_resync().
+ *
+ * @param phy_ctrl	pointer to the current phy controller
+ * @param offset	offset to read DQS
+ */
+static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
+				      unsigned int offset)
+{
+	writel(offset, &phy_ctrl->phy_con4);
+	ddr_phy_set_do_resync(phy_ctrl);
+}
+
+/**
+ * Convert a 2s complement byte to a byte with a sign bit.
+ *
+ * NOTE: you shouldn't use normal math on the number returned by this function.
+ *   As an example, -10 = 0xf6.  After this function -10 = 0x8a.  If you wanted
+ *   to do math and get the average of 10 and -10 (should be 0):
+ *     0x8a + 0xa = 0x94 (-108)
+ *     0x94 / 2   = 0xca (-54)
+ *   ...and 0xca = sign bit plus 0x4a, or -74
+ *
+ * Also note that you lose the ability to represent -128 since there are two
+ * representations of 0.
+ *
+ * @param b	The byte to convert in two's complement.
+ * @return	The 7-bit value + sign bit.
+ */
+
+unsigned char make_signed_byte(signed char b)
+{
+	if (b < 0)
+		return 0x80 | -b;
+	else
+		return b;
+}
+
+/**
+ * Test various shifts starting at 'start' and going to 'end'.
+ *
+ * For each byte lane, we'll walk through shift starting at 'start' and going
+ * to 'end' (inclusive).  When we are finally able to read the test pattern
+ * we'll store the value in the results array.
+ *
+ * @param phy_ctrl		pointer to the current phy controller
+ * @param ch			channel number
+ * @param start			the start shift.  -127 to 127
+ * @param end			the end shift.  -127 to 127
+ * @param results		we'll store results for each byte lane.
+ */
+
+void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
+		 int start, int end, int results[NUM_BYTE_LANES])
+{
+	int incr = (start < end) ? 1 : -1;
+	int byte_lane;
+
+	for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
+		int shift;
+
+		dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
+		results[byte_lane] = DEFAULT_DQS;
+
+		for (shift = start; shift != (end + incr); shift += incr) {
+			unsigned int byte_offsetr;
+			unsigned int offsetr;
+
+			byte_offsetr = make_signed_byte(shift);
+
+			offsetr = dmc_get_read_offset_value(phy_ctrl);
+			offsetr &= ~(0xFF << (8 * byte_lane));
+			offsetr |= (byte_offsetr << (8 * byte_lane));
+			dmc_set_read_offset_value(phy_ctrl, offsetr);
+
+			if (dmc_valid_window_test_vector(ch, byte_lane)) {
+				results[byte_lane] = shift;
+				break;
+			}
+		}
+	}
+}
+
+/**
+ * This function performs SW read leveling to compensate DQ-DQS skew at
+ * receiver it first finds the optimal read offset value on each DQS
+ * then applies the value to PHY.
+ *
+ * Read offset value has its min margin and max margin. If read offset
+ * value exceeds its min or max margin, read data will have corruption.
+ * To avoid this we are doing sw read leveling.
+ *
+ * SW read leveling is:
+ * 1> Finding offset value's left_limit and right_limit
+ * 2> and calculate its center value
+ * 3> finally programs that center value to PHY
+ * 4> then PHY gets its optimal offset value.
+ *
+ * @param phy_ctrl		pointer to the current phy controller
+ * @param ch			channel number
+ * @param coarse_lock_val	The coarse lock value read from PHY_CON13.
+ *				(0 - 0x7f)
+ */
+static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
+				      int ch, unsigned int coarse_lock_val)
+{
+	unsigned int offsetr_cent;
+	int byte_lane;
+	int left_limit;
+	int right_limit;
+	int left[NUM_BYTE_LANES];
+	int right[NUM_BYTE_LANES];
+	int i;
+
+	/* Fill the memory with test patterns */
+	for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
+		writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
+
+	/* Figure out the limits we'll test with; keep -127 < limit < 127 */
+	left_limit = DEFAULT_DQS - coarse_lock_val;
+	right_limit = DEFAULT_DQS + coarse_lock_val;
+	if (right_limit > 127)
+		right_limit = 127;
+
+	/* Fill in the location where reads were OK from left and right */
+	test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
+	test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
+
+	/* Make a final value by taking the center between the left and right */
+	offsetr_cent = 0;
+	for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
+		int temp_center;
+		unsigned int vmwc;
+
+		temp_center = (left[byte_lane] + right[byte_lane]) / 2;
+		vmwc = make_signed_byte(temp_center);
+		offsetr_cent |= vmwc << (8 * byte_lane);
+	}
+	dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
+}
+
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 {
 	struct exynos5420_clock *clk =
 		(struct exynos5420_clock *)samsung_get_base_clock();
@@ -231,7 +447,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
 	struct exynos5420_dmc *drex0, *drex1;
 	struct exynos5420_tzasc *tzasc0, *tzasc1;
+	struct exynos5_power *pmu;
 	uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+	uint32_t lock0_info, lock1_info;
 	int chip;
 	int i;
 
@@ -244,6 +462,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
 	tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
 							+ DMC_OFFSET);
+	pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
 
 	/* Enable PAUSE for DREX */
 	setbits_le32(&clk->pause, ENABLE_BIT);
@@ -394,7 +613,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		 */
 		dmc_config_mrs(mem, &drex0->directcmd);
 		dmc_config_mrs(mem, &drex1->directcmd);
-	} else {
+	}
+
+	/*
+	 * Get PHY_CON13 from both phys.  Gate CLKM around reading since
+	 * PHY_CON13 is glitchy when CLKM is running.  We're paranoid and
+	 * wait until we get a "fine lock", though a coarse lock is probably
+	 * OK (we only use the coarse numbers below).  We try to gate the
+	 * clock for as short a time as possible in case SDRAM is somehow
+	 * sensitive.  sdelay(10) in the loop is arbitrary to make sure
+	 * there is some time for PHY_CON13 to get updated.  In practice
+	 * no delay appears to be needed.
+	 */
+	val = readl(&clk->gate_bus_cdrex);
+	while (true) {
+		writel(val & ~0x1, &clk->gate_bus_cdrex);
+		lock0_info = readl(&phy0_ctrl->phy_con13);
+		writel(val, &clk->gate_bus_cdrex);
+
+		if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
+			break;
+
+		sdelay(10);
+	}
+	while (true) {
+		writel(val & ~0x2, &clk->gate_bus_cdrex);
+		lock1_info = readl(&phy1_ctrl->phy_con13);
+		writel(val, &clk->gate_bus_cdrex);
+
+		if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
+			break;
+
+		sdelay(10);
+	}
+
+	if (!reset) {
 		/*
 		 * During Suspend-Resume & S/W-Reset, as soon as PMU releases
 		 * pad retention, CKE goes high. This causes memory contents
@@ -445,15 +698,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
 		writel(val, &phy1_ctrl->phy_con1);
 
-		n_lock_r = readl(&phy0_ctrl->phy_con13);
-		n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
 		n_lock_r = readl(&phy0_ctrl->phy_con12);
 		n_lock_r &= ~CTRL_DLL_ON;
 		n_lock_r |= n_lock_w_phy0;
 		writel(n_lock_r, &phy0_ctrl->phy_con12);
 
-		n_lock_r = readl(&phy1_ctrl->phy_con13);
-		n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
 		n_lock_r = readl(&phy1_ctrl->phy_con12);
 		n_lock_r &= ~CTRL_DLL_ON;
 		n_lock_r |= n_lock_w_phy1;
@@ -482,7 +733,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(val, &phy1_ctrl->phy_con1);
 
 		writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
-		i = TIMEOUT;
+		i = TIMEOUT_US;
 		while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
 			RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
@@ -497,7 +748,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
 
 		writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
-		i = TIMEOUT;
+		i = TIMEOUT_US;
 		while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
 			RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
@@ -522,77 +773,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			       &drex1->directcmd);
 		}
 
-		if (mem->read_leveling_enable) {
-			/* Set Read DQ Calibration */
-			val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
-			for (chip = 0; chip < mem->chips_to_configure; chip++) {
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex0->directcmd);
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex1->directcmd);
-			}
-
-			val = readl(&phy0_ctrl->phy_con1);
-			val |= READ_LEVELLING_DDR3;
-			writel(val, &phy0_ctrl->phy_con1);
-			val = readl(&phy1_ctrl->phy_con1);
-			val |= READ_LEVELLING_DDR3;
-			writel(val, &phy1_ctrl->phy_con1);
-
-			val = readl(&phy0_ctrl->phy_con2);
-			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
-			writel(val, &phy0_ctrl->phy_con2);
-			val = readl(&phy1_ctrl->phy_con2);
-			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
-			writel(val, &phy1_ctrl->phy_con2);
-
-			setbits_le32(&drex0->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			i = TIMEOUT;
-			while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
-				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
-				/*
-				 * TODO(waihong): Comment on how long this take
-				 * to timeout
-				 */
-				sdelay(100);
-				i--;
-			}
-			if (!i)
-				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-
-			clrbits_le32(&drex0->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			setbits_le32(&drex1->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			i = TIMEOUT;
-			while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
-				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
-				/*
-				 * TODO(waihong): Comment on how long this take
-				 * to timeout
-				 */
-				sdelay(100);
-				i--;
-			}
-			if (!i)
-				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-
-			clrbits_le32(&drex1->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-
-			val = (0x3 << DIRECT_CMD_BANK_SHIFT);
-			for (chip = 0; chip < mem->chips_to_configure; chip++) {
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex0->directcmd);
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex1->directcmd);
-			}
-
-			update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
-			update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
-		}
-
 		/* Common Settings for Leveling */
 		val = PHY_CON12_RESET_VAL;
 		writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
@@ -602,6 +782,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
 	}
 
+	/*
+	 * Do software read leveling
+	 *
+	 * Do this before we turn on auto refresh since the auto refresh can
+	 * be in conflict with the resync operation that's part of setting
+	 * read leveling.
+	 */
+	if (!reset) {
+		/* restore calibrated value after resume */
+		dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
+		dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
+	} else {
+		software_find_read_offset(phy0_ctrl, 0,
+					  CTRL_LOCK_COARSE(lock0_info));
+		software_find_read_offset(phy1_ctrl, 1,
+					  CTRL_LOCK_COARSE(lock1_info));
+		/* save calibrated value to restore after resume */
+		writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
+		writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
+	}
+
 	/* Send PALL command */
 	dmc_config_prech(mem, &drex0->directcmd);
 	dmc_config_prech(mem, &drex1->directcmd);
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 53b0ace6e3..3242093855 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -282,8 +282,12 @@
 #define PHY_CON12_VAL		0x10107F50
 #define CTRL_START		(1 << 6)
 #define CTRL_DLL_ON		(1 << 5)
+#define CTRL_LOCK_COARSE_OFFSET	10
+#define CTRL_LOCK_COARSE_MASK	(0x7F << CTRL_LOCK_COARSE_OFFSET)
+#define CTRL_LOCK_COARSE(x)	(((x) & CTRL_LOCK_COARSE_MASK) >> \
+				 CTRL_LOCK_COARSE_OFFSET)
 #define CTRL_FORCE_MASK		(0x7F << 8)
-#define CTRL_LOCK_COARSE_MASK	(0x7F << 10)
+#define CTRL_FINE_LOCKED	0x7
 
 #define CTRL_OFFSETD_RESET_VAL	0x8
 #define CTRL_OFFSETD_VAL	0x7F
@@ -431,10 +435,10 @@
 
 /*
  * Definitions that differ with SoC's.
- * Below is the part defining macros for smdk5250.
- * Else part introduces macros for smdk5420.
+ * Below is the part defining macros for Exynos5250.
+ * Else part introduces macros for Exynos5420.
  */
-#ifndef CONFIG_SMDK5420
+#ifndef CONFIG_EXYNOS5420
 
 /* APLL_CON1 */
 #define APLL_CON1_VAL	(0x00203800)
@@ -890,16 +894,11 @@ enum {
 /*
  * Memory variant specific initialization code for DDR3
  *
- * @param mem		Memory timings for this memory type.
- * @param mem_iv_size	Memory interleaving size is a configurable parameter
- *			which the DMC uses to decide how to split a memory
- *			chunk into smaller chunks to support concurrent
- *			accesses; may vary across boards.
+ * @param mem          Memory timings for this memory type.
  * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-			int reset);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
 
 /* Memory variant specific initialization code for LPDDR3 */
 void lpddr3_mem_ctrl_init(void);
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 11fe5b8d04..83e1dcfc1e 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -39,6 +39,7 @@ enum {
 	DO_CLOCKS	= 1 << 1,
 	DO_MEM_RESET	= 1 << 2,
 	DO_UART		= 1 << 3,
+	DO_POWER	= 1 << 4,
 };
 
 int do_lowlevel_init(void)
@@ -60,9 +61,12 @@ int do_lowlevel_init(void)
 		break;
 	default:
 		/* This is a normal boot (not a wake from sleep) */
-		actions = DO_CLOCKS | DO_MEM_RESET;
+		actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
 	}
 
+	if (actions & DO_POWER)
+		set_ps_hold_ctrl();
+
 	if (actions & DO_CLOCKS) {
 		system_clock_init();
 		mem_ctrl_init(actions & DO_MEM_RESET);
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index ee7c2e5a4b..86a0c75326 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -573,15 +573,26 @@ static void exynos4_i2c_config(int peripheral, int flags)
 static int exynos4_mmc_config(int peripheral, int flags)
 {
 	int i, start = 0, start_ext = 0;
+	unsigned int func, ext_func;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
 		start = EXYNOS4_GPIO_K00;
 		start_ext = EXYNOS4_GPIO_K13;
+		func = S5P_GPIO_FUNC(0x2);
+		ext_func = S5P_GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC2:
 		start = EXYNOS4_GPIO_K20;
 		start_ext = EXYNOS4_GPIO_K33;
+		func = S5P_GPIO_FUNC(0x2);
+		ext_func = S5P_GPIO_FUNC(0x3);
+		break;
+	case PERIPH_ID_SDMMC4:
+		start = EXYNOS4_GPIO_K00;
+		start_ext = EXYNOS4_GPIO_K13;
+		func = S5P_GPIO_FUNC(0x3);
+		ext_func = S5P_GPIO_FUNC(0x4);
 		break;
 	default:
 		return -1;
@@ -589,13 +600,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
 	for (i = start; i < (start + 7); i++) {
 		if (i == (start + 2))
 			continue;
-		gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(i,  func);
 		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
+	/* SDMMC2 do not use 8bit mode at exynos4 */
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = start_ext; i < (start_ext + 4); i++) {
-			gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x3));
+			gpio_cfg_pin(i,  ext_func);
 			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
@@ -676,15 +688,26 @@ static void exynos4x12_i2c_config(int peripheral, int flags)
 static int exynos4x12_mmc_config(int peripheral, int flags)
 {
 	int i, start = 0, start_ext = 0;
+	unsigned int func, ext_func;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
 		start = EXYNOS4X12_GPIO_K00;
 		start_ext = EXYNOS4X12_GPIO_K13;
+		func = S5P_GPIO_FUNC(0x2);
+		ext_func = S5P_GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC2:
 		start = EXYNOS4X12_GPIO_K20;
 		start_ext = EXYNOS4X12_GPIO_K33;
+		func = S5P_GPIO_FUNC(0x2);
+		ext_func = S5P_GPIO_FUNC(0x3);
+		break;
+	case PERIPH_ID_SDMMC4:
+		start = EXYNOS4_GPIO_K00;
+		start_ext = EXYNOS4_GPIO_K13;
+		func = S5P_GPIO_FUNC(0x3);
+		ext_func = S5P_GPIO_FUNC(0x4);
 		break;
 	default:
 		return -1;
@@ -692,13 +715,13 @@ static int exynos4x12_mmc_config(int peripheral, int flags)
 	for (i = start; i < (start + 7); i++) {
 		if (i == (start + 2))
 			continue;
-		gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(i,  func);
 		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = start_ext; i < (start_ext + 4); i++) {
-			gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x3));
+			gpio_cfg_pin(i,  ext_func);
 			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
@@ -759,10 +782,10 @@ static int exynos4_pinmux_config(int peripheral, int flags)
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC4:
 		return exynos4_mmc_config(peripheral, flags);
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC3:
-	case PERIPH_ID_SDMMC4:
 		debug("SDMMC device %d not implemented\n", peripheral);
 		return -1;
 	default:
@@ -794,10 +817,10 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC4:
 		return exynos4x12_mmc_config(peripheral, flags);
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC3:
-	case PERIPH_ID_SDMMC4:
 		debug("SDMMC device %d not implemented\n", peripheral);
 		return -1;
 	default:
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index 563abd750f..638ee0b30b 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -112,6 +112,12 @@ static void exynos5_set_ps_hold_ctrl(void)
 			EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
 }
 
+/*
+ * Set ps_hold data driving value high
+ * This enables the machine to stay powered on
+ * after the initial power-on condition goes away
+ * (e.g. power button).
+ */
 void set_ps_hold_ctrl(void)
 {
 	if (cpu_is_exynos5())
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index ade45fd5d3..79166303d1 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include<common.h>
-#include<config.h>
+#include <common.h>
+#include <config.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index b1bd0224ea..c4af252110 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -5,7 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y	+= aemif.o
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c
deleted file mode 100644
index 9b26886dba..0000000000
--- a/arch/arm/cpu/armv7/keystone/aemif.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Keystone2: Asynchronous EMIF Configuration
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/emif_defs.h>
-
-#define AEMIF_CFG_SELECT_STROBE(v)	((v) ? 1 << 31 : 0)
-#define AEMIF_CFG_EXTEND_WAIT(v)	((v) ? 1 << 30 : 0)
-#define AEMIF_CFG_WR_SETUP(v)		(((v) & 0x0f) << 26)
-#define AEMIF_CFG_WR_STROBE(v)		(((v) & 0x3f) << 20)
-#define AEMIF_CFG_WR_HOLD(v)		(((v) & 0x07) << 17)
-#define AEMIF_CFG_RD_SETUP(v)		(((v) & 0x0f) << 13)
-#define AEMIF_CFG_RD_STROBE(v)		(((v) & 0x3f) << 7)
-#define AEMIF_CFG_RD_HOLD(v)		(((v) & 0x07) << 4)
-#define AEMIF_CFG_TURN_AROUND(v)	(((v) & 0x03) << 2)
-#define AEMIF_CFG_WIDTH(v)		(((v) & 0x03) << 0)
-
-#define set_config_field(reg, field, val)			\
-	do {							\
-		if (val != -1) {				\
-			reg &= ~AEMIF_CFG_##field(0xffffffff);	\
-			reg |=	AEMIF_CFG_##field(val);		\
-		}						\
-	} while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
-	unsigned long tmp;
-
-	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
-		tmp = __raw_readl(&davinci_emif_regs->nandfcr);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, &davinci_emif_regs->nandfcr);
-
-	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
-		tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
-		tmp |= (1 << cs);
-		__raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
-	}
-
-	tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
-
-	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
-	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
-	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
-	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
-	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
-	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
-	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
-	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
-	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
-	set_config_field(tmp, WIDTH,		cfg->width);
-
-	__raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
-	int cs;
-
-	for (cs = 0; cs < num_cs; cs++)
-		configure_async_emif(cs, config + cs);
-}
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 044015aed6..4df5ae1cae 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <ns16550.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
@@ -30,6 +31,14 @@ int arch_cpu_init(void)
 	share_all_segments(11); /* PCIE */
 #endif
 
+	/*
+	 * just initialise the COM2 port so that TI specific
+	 * UART register PWREMU_MGMT is initialized. Linux UART
+	 * driver doesn't handle this.
+	 */
+	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
+		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 5f5132f661..7695e16d36 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -22,6 +22,10 @@ obj-y	+= pipe3-phy.o
 obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 
+ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+obj-y	+= omap-cache.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y	+= boot-common.o
 obj-y	+= lowlevel_init.o
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index ba97d9ec56..5f50a19801 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -18,13 +18,8 @@
 #include <asm/emif.h>
 #include <asm/omap_common.h>
 #include <linux/compiler.h>
-#include <asm/cache.h>
 #include <asm/system.h>
 
-#define ARMV7_DCACHE_WRITEBACK  0xe
-#define	ARMV7_DOMAIN_CLIENT	1
-#define ARMV7_DOMAIN_MASK	(0x3 << 0)
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -263,40 +258,3 @@ int print_cpuinfo(void)
 	return 0;
 }
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
-	bd_t *bd = gd->bd;
-	int	i;
-
-	u32 start = bd->bi_dram[bank].start >> 20;
-	u32 size = bd->bi_dram[bank].size >> 20;
-	u32 end = start + size;
-
-	debug("%s: bank: %d\n", __func__, bank);
-	for (i = start; i < end; i++)
-		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-
-}
-
-void arm_init_domains(void)
-{
-	u32 reg;
-
-	reg = get_dacr();
-	/*
-	* Set DOMAIN to client access so that all permissions
-	* set in pagetables are validated by the mmu.
-	*/
-	reg &= ~ARMV7_DOMAIN_MASK;
-	reg |= ARMV7_DOMAIN_CLIENT;
-	set_dacr(reg);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 944ef840a1..5bc7e1f19b 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -121,7 +121,8 @@ void gpmc_init(void)
 	writel(0x00000008, &gpmc_cfg->sysconfig);
 	writel(0x00000000, &gpmc_cfg->irqstatus);
 	writel(0x00000000, &gpmc_cfg->irqenable);
-	writel(0x00000000, &gpmc_cfg->timeout_control);
+	/* disable timeout, set a safe reset value */
+	writel(0x00001ff0, &gpmc_cfg->timeout_control);
 #ifdef CONFIG_NOR
 	writel(0x00000200, &gpmc_cfg->config);
 #else
@@ -133,5 +134,6 @@ void gpmc_init(void)
 	writel(0, &gpmc_cfg->cs[0].config7);
 	sdelay(1000);
 	/* enable chip-select specific configurations */
-	enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
+	if (base != 0)
+		enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 }
diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c
new file mode 100644
index 0000000000..579bebf93f
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c
@@ -0,0 +1,56 @@
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Aneesh V	<aneesh@ti.com>
+ *	Steve Sakoman	<steve@sakoman.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARMV7_DCACHE_WRITEBACK  0xe
+#define ARMV7_DOMAIN_CLIENT	1
+#define ARMV7_DOMAIN_MASK	(0x3 << 0)
+
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	u32 start = bd->bi_dram[bank].start >> 20;
+	u32 size = bd->bi_dram[bank].size >> 20;
+	u32 end = start + size;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = start; i < end; i++)
+		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+}
+
+void arm_init_domains(void)
+{
+	u32 reg;
+
+	reg = get_dacr();
+	/*
+	* Set DOMAIN to client access so that all permissions
+	* set in pagetables are validated by the mmu.
+	*/
+	reg &= ~ARMV7_DOMAIN_MASK;
+	reg |= ARMV7_DOMAIN_CLIENT;
+	set_dacr(reg);
+}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 9bb1a1c8f9..667e77ff05 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -147,7 +147,7 @@ void secure_unlock_mem(void)
  *		configure secure registers and exit secure world
  *              general use.
  *****************************************************************************/
-void secureworld_exit()
+void secureworld_exit(void)
 {
 	unsigned long i;
 
@@ -178,7 +178,7 @@ void secureworld_exit()
  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
  *              general use.
  *****************************************************************************/
-void try_unlock_memory()
+void try_unlock_memory(void)
 {
 	int mode;
 	int in_sdram = is_running_in_sdram();
@@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void)
 	omap3_update_aux_cr(0, 0x2);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
index e649409654..1832affa5b 100644
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ b/arch/arm/cpu/armv7/omap3/mem.c
@@ -21,17 +21,6 @@
 struct gpmc *gpmc_cfg;
 
 #if defined(CONFIG_CMD_NAND)
-#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-	SMNAND_GPMC_CONFIG1,
-	SMNAND_GPMC_CONFIG2,
-	SMNAND_GPMC_CONFIG3,
-	SMNAND_GPMC_CONFIG4,
-	SMNAND_GPMC_CONFIG5,
-	SMNAND_GPMC_CONFIG6,
-	0,
-};
-#else
 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG1,
 	M_NAND_GPMC_CONFIG2,
@@ -40,7 +29,6 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG5,
 	M_NAND_GPMC_CONFIG6, 0
 };
-#endif
 #endif /* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_CMD_ONENAND)
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index cbe1d406df..eb33f2c5fb 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
 
 obj-y	:= lowlevel_init.o
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 2f1c7160f1..5268f2c708 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -14,3 +14,27 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
+defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 0000000000..a820b1b1bf
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,209 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/scan_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+		(void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+	uint32_t scanmgr_status;
+
+	scanmgr_status = readl(&scan_manager_base->stat);
+
+	/* Poll the engine until the scan engine is inactive */
+	while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+	      (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+		max_iter--;
+		if (max_iter > 0)
+			scanmgr_status = readl(&scan_manager_base->stat);
+		else
+			return 0;
+	}
+	return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+	uint32_t io_scan_chain_id,
+	uint32_t io_scan_chain_len_in_bits,
+	const uint32_t *iocsr_scan_chain)
+{
+	uint16_t tdi_tdo_header;
+	uint32_t io_program_iter;
+	uint32_t io_scan_chain_data_residual;
+	uint32_t residual;
+	uint32_t i;
+	uint32_t index = 0;
+
+	/*
+	 * De-assert reinit if the IO scan chain is intended for HIO. In
+	 * this, its the chain 3.
+	 */
+	if (io_scan_chain_id == 3)
+		clrbits_le32(&freeze_controller_base->hioctrl,
+			     SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+	/*
+	 * Check if the scan chain engine is inactive and the
+	 * WFIFO is empty before enabling the IO scan chain
+	 */
+	if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+		return 1;
+
+	/*
+	 * Enable IO Scan chain based on scan chain id
+	 * Note: only one chain can be enabled at a time
+	 */
+	setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+	/*
+	 * Calculate number of iteration needed for full 128-bit (4 x32-bits)
+	 * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+	 */
+	io_program_iter	= io_scan_chain_len_in_bits >>
+		IO_SCAN_CHAIN_128BIT_SHIFT;
+	io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+		IO_SCAN_CHAIN_128BIT_MASK;
+
+	/* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+	tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
+		(TDI_TDO_MAX_PAYLOAD <<	TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+	/* Program IO scan chain in 128-bit iteration */
+	for (i = 0; i < io_program_iter; i++) {
+		/* write TDI_TDO packet header to scan manager */
+		writel(tdi_tdo_header,	&scan_manager_base->fifo_double_byte);
+
+		/* calculate array index. Multiply by 4 as write 4 x 32bits */
+		index = i * 4;
+
+		/* write 4 successive 32-bit IO scan chain data into WFIFO */
+		writel(iocsr_scan_chain[index],
+		       &scan_manager_base->fifo_quad_byte);
+		writel(iocsr_scan_chain[index + 1],
+		       &scan_manager_base->fifo_quad_byte);
+		writel(iocsr_scan_chain[index + 2],
+		       &scan_manager_base->fifo_quad_byte);
+		writel(iocsr_scan_chain[index + 3],
+		       &scan_manager_base->fifo_quad_byte);
+
+		/*
+		 * Check if the scan chain engine has completed the
+		 * IO scan chain data shifting
+		 */
+		if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+			goto error;
+	}
+
+	/* Calculate array index for final TDI_TDO packet */
+	index = io_program_iter * 4;
+
+	/* Final TDI_TDO packet if any */
+	if (io_scan_chain_data_residual) {
+		/*
+		 * Calculate number of quad bytes FIFO write
+		 * needed for the final TDI_TDO packet
+		 */
+		io_program_iter	= io_scan_chain_data_residual >>
+			IO_SCAN_CHAIN_32BIT_SHIFT;
+
+		/*
+		 * Construct TDI_TDO packet for remaining IO
+		 * scan chain (2 bytes)
+		 */
+		tdi_tdo_header	= TDI_TDO_HEADER_FIRST_BYTE |
+			((io_scan_chain_data_residual - 1) <<
+			TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+		/*
+		 * Program the last part of IO scan chain write TDI_TDO packet
+		 * header (2 bytes) to scan manager
+		 */
+		writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte);
+
+		for (i = 0; i < io_program_iter; i++) {
+			/*
+			 * write remaining scan chain data into scan
+			 * manager WFIFO with 4 bytes write
+			*/
+			writel(iocsr_scan_chain[index + i],
+			       &scan_manager_base->fifo_quad_byte);
+		}
+
+		index += io_program_iter;
+		residual = io_scan_chain_data_residual &
+			IO_SCAN_CHAIN_32BIT_MASK;
+
+		if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) {
+			/*
+			 * write the last 4B scan chain data
+			 * into scan manager WFIFO
+			 */
+			writel(iocsr_scan_chain[index],
+			       &scan_manager_base->fifo_quad_byte);
+		} else {
+			/*
+			 * write the remaining 1 - 3 bytes scan chain
+			 * data into scan manager WFIFO byte by byte
+			 * to prevent JTAG engine shifting unused data
+			 * from the FIFO and mistaken the data as a
+			 * valid command (even though unused bits are
+			 * set to 0, but just to prevent hardware
+			 * glitch)
+			 */
+			for (i = 0; i < residual; i += 8) {
+				writel(((iocsr_scan_chain[index] >> i)
+					& IO_SCAN_CHAIN_BYTE_MASK),
+					&scan_manager_base->fifo_single_byte);
+			}
+		}
+
+		/*
+		 * Check if the scan chain engine has completed the
+		 * IO scan chain data shifting
+		 */
+		if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+			goto error;
+	}
+
+	/* Disable IO Scan chain when configuration done*/
+	clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+	return 0;
+
+error:
+	/* Disable IO Scan chain when error detected */
+	clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+	return 1;
+}
+
+int scan_mgr_configure_iocsr(void)
+{
+	int status = 0;
+
+	/* configure the IOCSR through scan chain */
+	status |= scan_mgr_io_scan_chain_prg(0,
+		CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table);
+	status |= scan_mgr_io_scan_chain_prg(1,
+		CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table);
+	status |= scan_mgr_io_scan_chain_prg(2,
+		CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table);
+	status |= scan_mgr_io_scan_chain_prg(3,
+		CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table);
+	return status;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 2ae88bbd04..4bed19d0a7 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -121,6 +121,10 @@ void spl_board_init(void)
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);
 
+	/* configure the IOCSR / IO buffer settings */
+	if (scan_mgr_configure_iocsr())
+		hang();
+
 	/* configure the pin muxing through system manager */
 	sysmgr_pinmux_init();
 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
index 488f0c639d..fd77f3f0ef 100644
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ b/arch/arm/cpu/armv7/tegra20/display.c
@@ -328,7 +328,7 @@ static int tegra_display_decode_config(const void *blob,
 	rgb = fdt_subnode_offset(blob, node, "rgb");
 
 	config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
-	if (!config->panel_node < 0) {
+	if (config->panel_node < 0) {
 		debug("%s: Cannot find panel information\n", __func__);
 		return -1;
 	}
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds
index 69500a64e2..4dc9bb0102 100644
--- a/arch/arm/cpu/armv7/zynq/u-boot.lds
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -18,6 +18,7 @@ SECTIONS
 	.text :
 	{
 		*(.__image_copy_start)
+		*(.vectors)
 		CPUDIR/start.o (.text*)
 		*(.text*)
 	}