Merge branch 'master' of git://git.denx.de/u-boot-arm

30 files changed, 2434 insertions, 457 deletions

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 232118d7f4..703ce8c640 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -21,6 +21,11 @@ endif
 ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
 obj-y	+= nonsec_virt.o
 obj-y	+= virt-v7.o
+obj-y	+= virt-dt.o
+endif
+
+ifneq ($(CONFIG_ARMV7_PSCI),)
+obj-y	+= psci.o
 endif
 
 obj-$(CONFIG_KONA) += kona-common/
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index c4af252110..f8519c0403 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -8,9 +8,12 @@
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
+obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
-obj-y	+= keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y	+= msmc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 obj-y	+= ddr3.o
+obj-y	+= keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
new file mode 100644
index 0000000000..42092e1060
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case DDR3_PLL:
+			ret = external_clk[ddr3_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:      return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
+	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
new file mode 100644
index 0000000000..96a9f72886
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
@@ -0,0 +1,113 @@
+/*
+ * Keystone2: get clk rate for K2HK
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				 PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case TETRIS_PLL:
+			ret = external_clk[tetris_clk];
+			reg = KS2_ARMPLLCTL0;
+			break;
+		case DDR3A_PLL:
+			ret = external_clk[ddr3a_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		case DDR3B_PLL:
+			ret = external_clk[ddr3b_clk];
+			reg = KS2_DDR3BPLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:	return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
+	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
+	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
+	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index bfa4c9d8f6..03c1d9f660 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -8,9 +8,6 @@
  */
 
 #include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
@@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data)
 	}
 }
 
-struct pll_regs {
-	u32	reg0, reg1;
-};
-
-static const struct pll_regs pll_regs[] = {
-	[CORE_PLL]	= { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
-	[PASS_PLL]	= { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
-	[TETRIS_PLL]	= { K2HK_ARMPLLCTL0,  K2HK_ARMPLLCTL1},
-	[DDR3A_PLL]	= { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
-	[DDR3B_PLL]	= { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
-};
-
-/* Fout = Fref * NF(mult) / NR(prediv) / OD */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(K2HK_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				 PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = K2HK_PASSPLLCTL0;
-			break;
-		case TETRIS_PLL:
-			ret = external_clk[tetris_clk];
-			reg = K2HK_ARMPLLCTL0;
-			break;
-		case DDR3A_PLL:
-			ret = external_clk[ddr3a_clk];
-			reg = K2HK_DDR3APLLCTL0;
-			break;
-		case DDR3B_PLL:
-			ret = external_clk[ddr3b_clk];
-			reg = K2HK_DDR3BPLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:	return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
-	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
-	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
-	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-	return 0;
-}
-
 void init_pll(const struct pll_init_data *data)
 {
 	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
@@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data)
 		tmp = pllctl_reg_read(data->pll, secctl);
 
 		if (tmp & (PLLCTL_BYPASS)) {
-			setbits_le32(pll_regs[data->pll].reg1,
+			setbits_le32(keystone_pll_regs[data->pll].reg1,
 				     BIT(MAIN_ENSAT_OFFSET));
 
 			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
@@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data)
 
 		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
 
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
-				(pllm << 6));
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLLM_MULT_HI_SMASK, (pllm << 6));
 
 		/* Set the BWADJ     (12 bit field)  */
 		tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLL_BWADJ_LO_SMASK,
 				(tmp_ctl << PLL_BWADJ_LO_SHIFT));
-		clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+				PLL_BWADJ_HI_MASK,
 				(tmp_ctl >> 8));
 
 		/*
 		 * Set the pll divider (6 bit field) *
 		 * PLLD[5:0] is located in MAINPLLCTL0
 		 */
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLL_DIV_MASK, plld);
 
 		/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
 		pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
@@ -206,17 +106,18 @@ void init_pll(const struct pll_init_data *data)
 
 		tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
 
+#ifndef CONFIG_SOC_K2E
 	} else if (data->pll == TETRIS_PLL) {
 		bwadj = pllm >> 1;
 		/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
-		setbits_le32(pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
+		setbits_le32(keystone_pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
 		/*
 		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
-		setbits_le32(pll_regs[data->pll].reg1 ,
+		setbits_le32(keystone_pll_regs[data->pll].reg1 ,
 			     PLL_PLLRST | PLLCTL_ENSAT);
 
 		/*
@@ -229,13 +130,13 @@ void init_pll(const struct pll_init_data *data)
 			(pllm << 6) |
 			(plld & PLL_DIV_MASK) |
 			(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
-		__raw_writel(tmp, pll_regs[data->pll].reg0);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 
 		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 		tmp &= ~(PLL_BWADJ_HI_MASK);
 		tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
-		__raw_writel(tmp, pll_regs[data->pll].reg1);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 		/*
 		 * 5 Wait for at least 5 us based on the reference
 		 * clock (PLL reset time)
@@ -243,26 +144,27 @@ void init_pll(const struct pll_init_data *data)
 		sdelay(21000);	/* Wait for a minimum of 7 us*/
 
 		/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
-		clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+		clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
 		/*
 		 * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
 		 * (PLL lock time)
 		 */
 		sdelay(105000);
 		/* 8 disable bypass */
-		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 		/*
 		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
+#endif
 	} else {
-		setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+		setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
 		/*
 		 * process keeps state of Bypass bit while programming
 		 * all other DDR PLL settings
 		 */
-		tmp = __raw_readl(pll_regs[data->pll].reg0);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
 		tmp &= PLLCTL_BYPASS;	/* clear everything except Bypass */
 
 		/*
@@ -274,10 +176,10 @@ void init_pll(const struct pll_init_data *data)
 			(pllm << PLL_MULT_SHIFT) |
 			(plld & PLL_DIV_MASK) |
 			(pllod << PLL_CLKOD_SHIFT);
-		__raw_writel(tmp, pll_regs[data->pll].reg0);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 
 		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 		tmp &= ~(PLL_BWADJ_HI_MASK);
 		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 
@@ -285,20 +187,20 @@ void init_pll(const struct pll_init_data *data)
 		if (data->pll == PASS_PLL)
 			tmp |= PLLCTL_PAPLL;
 
-		__raw_writel(tmp, pll_regs[data->pll].reg1);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 
 		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
 		tmp = PLL_PLLRST;
 		/* Set RESET bit = 1 */
-		setbits_le32(pll_regs[data->pll].reg1, tmp);
+		setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 		/* Wait for a minimum of 7 us*/
 		sdelay(21000);
 		/* Clear RESET bit */
-		clrbits_le32(pll_regs[data->pll].reg1, tmp);
+		clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 		sdelay(105000);
 
 		/* clear BYPASS (Enable PLL Mode) */
-		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 		sdelay(21000);	/* Wait for a minimum of 7 us*/
 	}
 
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index afd30f3853..d97c95be11 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -14,10 +14,10 @@
 #include <asm/arch/psc_defs.h>
 
 struct pll_init_data cmd_pll_data = {
-	.pll			= MAIN_PLL,
-	.pll_m			= 16,
-	.pll_d			= 1,
-	.pll_od			= 2,
+	.pll = MAIN_PLL,
+	.pll_m = 16,
+	.pll_d = 1,
+	.pll_od = 2,
 };
 
 int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	if (strncmp(argv[1], "pa", 2) == 0)
 		cmd_pll_data.pll = PASS_PLL;
+#ifndef CONFIG_SOC_K2E
 	else if (strncmp(argv[1], "arm", 3) == 0)
 		cmd_pll_data.pll = TETRIS_PLL;
+#endif
+#ifdef CONFIG_SOC_K2HK
 	else if (strncmp(argv[1], "ddr3a", 5) == 0)
 		cmd_pll_data.pll = DDR3A_PLL;
 	else if (strncmp(argv[1], "ddr3b", 5) == 0)
 		cmd_pll_data.pll = DDR3B_PLL;
+#else
+	else if (strncmp(argv[1], "ddr3", 4) == 0)
+		cmd_pll_data.pll = DDR3_PLL;
+#endif
 	else
 		goto pll_cmd_usage;
 
@@ -51,11 +58,20 @@ pll_cmd_usage:
 	return cmd_usage(cmdtp);
 }
 
+#ifdef CONFIG_SOC_K2HK
 U_BOOT_CMD(
 	pllset,	5,	0,	do_pll_cmd,
 	"set pll multiplier and pre divider",
 	"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
 );
+#endif
+#ifdef CONFIG_SOC_K2E
+U_BOOT_CMD(
+	pllset, 5,      0,      do_pll_cmd,
+	"set pll multiplier and pre divider",
+	"<pa|ddr3> <mult> <div> <OD>\n"
+);
+#endif
 
 int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -79,7 +95,12 @@ U_BOOT_CMD(
 	getclk,	2,	0,	do_getclk_cmd,
 	"get clock rate",
 	"<clk index>\n"
-	"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+#ifdef CONFIG_SOC_K2HK
+	"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
+#endif
+#ifdef CONFIG_SOC_K2E
+	"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
+#endif
 );
 
 int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 4875db76a3..2391e794e8 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -7,10 +7,11 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#include <asm/arch/hardware.h>
 #include <asm/io.h>
+#include <common.h>
+#include <asm/arch/ddr3.h>
 
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
 	unsigned int tmp;
 
@@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 		;
 }
 
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 {
 	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
 	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
@@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
 	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
 }
+
+void ddr3_reset_ddrphy(void)
+{
+	u32 tmp;
+
+	/* Assert DDR3A  PHY reset */
+	tmp = readl(KS2_DDR3APLLCTL1);
+	tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+	writel(tmp, KS2_DDR3APLLCTL1);
+
+	/* wait 10us to catch the reset */
+	udelay(10);
+
+	/* Release DDR3A PHY reset */
+	tmp = readl(KS2_DDR3APLLCTL1);
+	tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
+	__raw_writel(tmp, KS2_DDR3APLLCTL1);
+}
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 4df5ae1cae..a8f8aee8ab 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -10,13 +10,14 @@
 #include <common.h>
 #include <ns16550.h>
 #include <asm/io.h>
+#include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 
 void chip_configuration_unlock(void)
 {
-	__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
-	__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
 int arch_cpu_init(void)
@@ -24,11 +25,12 @@ int arch_cpu_init(void)
 	chip_configuration_unlock();
 	icache_enable();
 
-#ifdef CONFIG_SOC_K2HK
-	share_all_segments(8);
-	share_all_segments(9);
-	share_all_segments(10); /* QM PDSP */
-	share_all_segments(11); /* PCIE */
+	msmc_share_all_segments(8);  /* TETRIS */
+	msmc_share_all_segments(9);  /* NETCP */
+	msmc_share_all_segments(10); /* QM PDSP */
+	msmc_share_all_segments(11); /* PCIE 0 */
+#ifdef CONFIG_SOC_K2E
+	msmc_share_all_segments(13); /* PCIE 1 */
 #endif
 
 	/*
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
new file mode 100644
index 0000000000..11a9357db4
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -0,0 +1,87 @@
+/*
+ * Keystone EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mon.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/hardware.h>
+
+/**
+ * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
+ * @ptr - array of data
+ * @length - lenght of data array
+ */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+	u32 i;
+
+	if (!(readl(KS2_DEVSTAT) & 0x1))
+		for (i = 0; i < length; i++, ptr++)
+			*ptr = cpu_to_be32(*ptr);
+
+	return 0;
+}
+
+static int turn_off_myself(void)
+{
+	printf("Turning off ourselves\r\n");
+	mon_power_off(0);
+
+	psc_disable_module(KS2_LPSC_TETRIS);
+	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+	asm volatile ("isb\n"
+		      "dsb\n"
+		      "wfi\n");
+
+	printf("What! Should not see that\n");
+	return 0;
+}
+
+static void turn_off_all_dsps(int num_dsps)
+{
+	int i;
+
+	for (i = 0; i < num_dsps; i++) {
+		if (psc_disable_module(i + KS2_LPSC_GEM_0))
+			printf("Cannot disable module for #%d DSP", i);
+
+		if (psc_disable_domain(i + 8))
+			printf("Cannot disable domain for #%d DSP", i);
+	}
+}
+
+int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	return turn_off_myself();
+}
+
+U_BOOT_CMD(
+	killme, 1,      0,      do_killme_cmd,
+	"turn off main ARM core",
+	"turn off main ARM core. Should not live after that :(\n"
+);
+
+int misc_init_r(void)
+{
+	char *env;
+	long ks2_debug = 0;
+
+	env = getenv("ks2_debug");
+
+	if (env)
+		ks2_debug = simple_strtol(env, NULL, 0);
+
+	if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
+		turn_off_all_dsps(KS2_NUM_DSPS);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index f3f1621d20..7d8e5978df 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/msmc.h>
 
 struct mpax {
 	u32	mpaxl;
@@ -56,9 +56,9 @@ struct msms_regs {
 };
 
 
-void share_all_segments(int priv_id)
+void msmc_share_all_segments(int priv_id)
 {
-	struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
 	int j;
 
 	for (j = 0; j < 8; j++) {
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
index c844dc84d5..fa5422f2e8 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -16,10 +16,6 @@
 #define DEVICE_REG32_R(addr)			__raw_readl((u32 *)(addr))
 #define DEVICE_REG32_W(addr, val)		__raw_writel(val, (u32 *)(addr))
 
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASE				K2HK_PSC_BASE
-#endif
-
 int psc_delay(void)
 {
 	udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
 	retry = 0;
 
 	do {
-		ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+		ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
 		ptstat = ptstat & (1 << domain_num);
 	} while ((ptstat != 0) && ((retry += psc_delay()) <
 		 PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
 	u32 domain_num;
 
 	/* Get the power domain associated with the module number */
-	domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+	domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
 				    PSC_REG_MDCFG(mod_num));
 	domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
 
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
 	 * Get the power domain associated with the module number, and reset
 	 * isolation functionality
 	 */
-	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
 	domain_num = PSC_REG_MDCFG_GET_PD(v);
 	reset_iso  = PSC_REG_MDCFG_GET_RESET_ISO(v);
 
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
 	 * change is made if the new state is power down.
 	 */
 	if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
-		pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+		pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
 				       PSC_REG_PDCTL(domain_num));
 		pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
 					       PSC_REG_VAL_PDCTL_NEXT_ON);
-		DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+		DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
 			       pdctl);
 	}
 
 	/* Set the next state for the module to enabled/disabled */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
 	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
 	/* Trigger the enable */
-	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
 	ptcmd |= (u32)(1<<domain_num);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
 	/* Wait on the complete */
 	return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the bit to apply reset */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
 		return 0;
 
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the bit to apply reset */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	if ((mdctl & 0x3f) == 0)
 		return 0;
 	mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
 	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
 }
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the reset isolation bit */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
-	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
 	if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
 		return 0;
 
@@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
 	u32 pdctl;
 	u32 ptcmd;
 
-	pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+	pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
 	pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
 	pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
 
-	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
 	ptcmd |= (u32)(1 << domain_num);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
 	return psc_wait(domain_num);
 }
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
index e07b64db9e..d4b0e9b163 100644
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ b/arch/arm/cpu/armv7/keystone/spl.c
@@ -18,10 +18,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_K2HK_EVM
 static struct pll_init_data spl_pll_config[] = {
 	CORE_PLL_799,
 	TETRIS_PLL_500,
 };
+#endif
+
+#ifdef CONFIG_K2E_EVM
+static struct pll_init_data spl_pll_config[] = {
+	CORE_PLL_800,
+};
+#endif
 
 void spl_init_keystone_plls(void)
 {
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 6367e09612..745670e549 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -10,10 +10,13 @@
 #include <linux/linkage.h>
 #include <asm/gic.h>
 #include <asm/armv7.h>
+#include <asm/proc-armv/ptrace.h>
 
 .arch_extension sec
 .arch_extension virt
 
+	.pushsection ._secure.text, "ax"
+
 	.align	5
 /* the vector table for secure state and HYP mode */
 _monitor_vectors:
@@ -22,43 +25,95 @@ _monitor_vectors:
 	adr pc, _secure_monitor
 	.word 0
 	.word 0
-	adr pc, _hyp_trap
+	.word 0
 	.word 0
 	.word 0
 
+.macro is_cpu_virt_capable	tmp
+	mrc	p15, 0, \tmp, c0, c1, 1		@ read ID_PFR1
+	and	\tmp, \tmp, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
+	cmp	\tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
+.endm
+
 /*
  * secure monitor handler
  * U-boot calls this "software interrupt" in start.S
  * This is executed on a "smc" instruction, we use a "smc #0" to switch
  * to non-secure state.
- * We use only r0 and r1 here, due to constraints in the caller.
+ * r0, r1, r2: passed to the callee
+ * ip: target PC
  */
 _secure_monitor:
-	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
-	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
-	orr	r1, r1, #0x31			@ enable NS, AW, FW bits
+#ifdef CONFIG_ARMV7_PSCI
+	ldr	r5, =_psci_vectors		@ Switch to the next monitor
+	mcr	p15, 0, r5, c12, c0, 1
+	isb
 
-#ifdef CONFIG_ARMV7_VIRT
-	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
-	and	r0, r0, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
-	cmp	r0, #(1 << CPUID_ARM_VIRT_SHIFT)
-	orreq	r1, r1, #0x100			@ allow HVC instruction
+	@ Obtain a secure stack, and configure the PSCI backend
+	bl	psci_arch_init
 #endif
 
-	mcr	p15, 0, r1, c1, c1, 0		@ write SCR (with NS bit set)
-
+	mrc	p15, 0, r5, c1, c1, 0		@ read SCR
+	bic	r5, r5, #0x4a			@ clear IRQ, EA, nET bits
+	orr	r5, r5, #0x31			@ enable NS, AW, FW bits
+						@ FIQ preserved for secure mode
+	mov	r6, #SVC_MODE			@ default mode is SVC
+	is_cpu_virt_capable r4
 #ifdef CONFIG_ARMV7_VIRT
-	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value
-	mcreq	p15, 4, r0, c12, c0, 0		@ write HVBAR
+	orreq	r5, r5, #0x100			@ allow HVC instruction
+	moveq	r6, #HYP_MODE			@ Enter the kernel as HYP
 #endif
 
-	movs	pc, lr				@ return to non-secure SVC
-
-_hyp_trap:
-	mrs	lr, elr_hyp	@ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
-	mov pc, lr				@ do no switch modes, but
-						@ return to caller
+	mcr	p15, 0, r5, c1, c1, 0		@ write SCR (with NS bit set)
+	isb
 
+	bne	1f
+
+	@ Reset CNTVOFF to 0 before leaving monitor mode
+	mrc	p15, 0, r4, c0, c1, 1		@ read ID_PFR1
+	ands	r4, r4, #CPUID_ARM_GENTIMER_MASK	@ test arch timer bits
+	movne	r4, #0
+	mcrrne	p15, 4, r4, r4, c14		@ Reset CNTVOFF to zero
+1:
+	mov	lr, ip
+	mov	ip, #(F_BIT | I_BIT | A_BIT)	@ Set A, I and F
+	tst	lr, #1				@ Check for Thumb PC
+	orrne	ip, ip, #T_BIT			@ Set T if Thumb
+	orr	ip, ip, r6			@ Slot target mode in
+	msr	spsr_cxfs, ip			@ Set full SPSR
+	movs	pc, lr				@ ERET to non-secure
+
+ENTRY(_do_nonsec_entry)
+	mov	ip, r0
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	smc	#0
+ENDPROC(_do_nonsec_entry)
+
+.macro get_cbar_addr	addr
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+	ldr	\addr, =CONFIG_ARM_GIC_BASE_ADDRESS
+#else
+	mrc	p15, 4, \addr, c15, c0, 0	@ read CBAR
+	bfc	\addr, #0, #15			@ clear reserved bits
+#endif
+.endm
+
+.macro get_gicd_addr	addr
+	get_cbar_addr	\addr
+	add	\addr, \addr, #GIC_DIST_OFFSET	@ GIC dist i/f offset
+.endm
+
+.macro get_gicc_addr	addr, tmp
+	get_cbar_addr	\addr
+	is_cpu_virt_capable \tmp
+	movne	\tmp, #GIC_CPU_OFFSET_A9	@ GIC CPU offset for A9
+	moveq	\tmp, #GIC_CPU_OFFSET_A15	@ GIC CPU offset for A15/A7
+	add	\addr, \addr, \tmp
+.endm
+
+#ifndef CONFIG_ARMV7_PSCI
 /*
  * Secondary CPUs start here and call the code for the core specific parts
  * of the non-secure and HYP mode transition. The GIC distributor specific
@@ -66,31 +121,21 @@ _hyp_trap:
  * Then they go back to wfi and wait to be woken up by the kernel again.
  */
 ENTRY(_smp_pen)
-	mrs	r0, cpsr
-	orr	r0, r0, #0xc0
-	msr	cpsr, r0			@ disable interrupts
-	ldr	r1, =_start
-	mcr	p15, 0, r1, c12, c0, 0		@ set VBAR
+	cpsid	i
+	cpsid	f
 
 	bl	_nonsec_init
-	mov	r12, r0				@ save GICC address
-#ifdef CONFIG_ARMV7_VIRT
-	bl	_switch_to_hyp
-#endif
-
-	ldr	r1, [r12, #GICC_IAR]		@ acknowledge IPI
-	str	r1, [r12, #GICC_EOIR]		@ signal end of interrupt
 
 	adr	r0, _smp_pen			@ do not use this address again
 	b	smp_waitloop			@ wait for IPIs, board specific
 ENDPROC(_smp_pen)
+#endif
 
 /*
  * Switch a core to non-secure state.
  *
  *  1. initialize the GIC per-core interface
  *  2. allow coprocessor access in non-secure modes
- *  3. switch the cpu mode (by calling "smc #0")
  *
  * Called from smp_pen by secondary cores and directly by the BSP.
  * Do not assume that the stack is available and only use registers
@@ -100,38 +145,23 @@ ENDPROC(_smp_pen)
  * though, but we check this in C before calling this function.
  */
 ENTRY(_nonsec_init)
-#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	ldr	r2, =CONFIG_ARM_GIC_BASE_ADDRESS
-#else
-	mrc	p15, 4, r2, c15, c0, 0		@ read CBAR
-	bfc	r2, #0, #15			@ clear reserved bits
-#endif
-	add	r3, r2, #GIC_DIST_OFFSET	@ GIC dist i/f offset
+	get_gicd_addr	r3
+
 	mvn	r1, #0				@ all bits to 1
 	str	r1, [r3, #GICD_IGROUPRn]	@ allow private interrupts
 
-	mrc	p15, 0, r0, c0, c0, 0		@ read MIDR
-	ldr	r1, =MIDR_PRIMARY_PART_MASK
-	and	r0, r0, r1			@ mask out variant and revision
+	get_gicc_addr	r3, r1
 
-	ldr	r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
-	cmp	r0, r1				@ check for Cortex-A7
-
-	ldr	r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
-	cmpne	r0, r1				@ check for Cortex-A15
-
-	movne	r1, #GIC_CPU_OFFSET_A9		@ GIC CPU offset for A9
-	moveq	r1, #GIC_CPU_OFFSET_A15		@ GIC CPU offset for A15/A7
-	add	r3, r2, r1			@ r3 = GIC CPU i/f addr
-
-	mov	r1, #1				@ set GICC_CTLR[enable]
+	mov	r1, #3				@ Enable both groups
 	str	r1, [r3, #GICC_CTLR]		@ and clear all other bits
 	mov	r1, #0xff
 	str	r1, [r3, #GICC_PMR]		@ set priority mask register
 
+	mrc	p15, 0, r0, c1, c1, 2
 	movw	r1, #0x3fff
-	movt	r1, #0x0006
-	mcr	p15, 0, r1, c1, c1, 2		@ NSACR = all copros to non-sec
+	movt	r1, #0x0004
+	orr	r0, r0, r1
+	mcr	p15, 0, r0, c1, c1, 2		@ NSACR = all copros to non-sec
 
 /* The CNTFRQ register of the generic timer needs to be
  * programmed in secure state. Some primary bootloaders / firmware
@@ -149,21 +179,9 @@ ENTRY(_nonsec_init)
 
 	adr	r1, _monitor_vectors
 	mcr	p15, 0, r1, c12, c0, 1		@ set MVBAR to secure vectors
-
-	mrc	p15, 0, ip, c12, c0, 0		@ save secure copy of VBAR
-
 	isb
-	smc	#0				@ call into MONITOR mode
-
-	mcr	p15, 0, ip, c12, c0, 0		@ write non-secure copy of VBAR
-
-	mov	r1, #1
-	str	r1, [r3, #GICC_CTLR]		@ enable non-secure CPU i/f
-	add	r2, r2, #GIC_DIST_OFFSET
-	str	r1, [r2, #GICD_CTLR]		@ allow private interrupts
 
 	mov	r0, r3				@ return GICC address
-
 	bx	lr
 ENDPROC(_nonsec_init)
 
@@ -175,18 +193,10 @@ ENTRY(smp_waitloop)
 	ldr	r1, [r1]
 	cmp	r0, r1			@ make sure we dont execute this code
 	beq	smp_waitloop		@ again (due to a spurious wakeup)
-	mov	pc, r1
+	mov	r0, r1
+	b	_do_nonsec_entry
 ENDPROC(smp_waitloop)
 .weak smp_waitloop
 #endif
 
-ENTRY(_switch_to_hyp)
-	mov	r0, lr
-	mov	r1, sp				@ save SVC copy of LR and SP
-	isb
-	hvc #0			 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
-	mov	sp, r1
-	mov	lr, r0				@ restore SVC copy of LR and SP
-
-	bx	lr
-ENDPROC(_switch_to_hyp)
+	.popsection
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 5f50a19801..1b4477f469 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -123,7 +123,8 @@ void s_init(void)
 	hw_data_init();
 
 #ifdef CONFIG_SPL_BUILD
-	if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+	if (warm_reset() &&
+	    (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
 		force_emif_self_refresh();
 #endif
 	watchdog_init();
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 5bc7e1f19b..fc4290c3c4 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -87,9 +87,13 @@ void gpmc_init(void)
 						STNOR_GPMC_CONFIG6,
 						STNOR_GPMC_CONFIG7
 						};
-	u32 size = GPMC_SIZE_16M;
 	u32 base = CONFIG_SYS_FLASH_BASE;
-#elif defined(CONFIG_NAND)
+	u32 size =	(CONFIG_SYS_FLASH_SIZE  > 0x08000000) ? GPMC_SIZE_256M :
+	/* > 64MB */	((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+	/* > 32MB */	((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
+	/* > 16MB */	((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
+	/* min 16MB */	GPMC_SIZE_16M)));
+#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
 /* configure GPMC for NAND */
 	const u32  gpmc_regs[GPMC_MAX_REG] = {	M_NAND_GPMC_CONFIG1,
 						M_NAND_GPMC_CONFIG2,
@@ -99,8 +103,9 @@ void gpmc_init(void)
 						M_NAND_GPMC_CONFIG6,
 						0
 						};
-	u32 size = GPMC_SIZE_256M;
 	u32 base = CONFIG_SYS_NAND_BASE;
+	u32 size = GPMC_SIZE_16M;
+
 #elif defined(CONFIG_CMD_ONENAND)
 	const u32 gpmc_regs[GPMC_MAX_REG] = {	ONENAND_GPMC_CONFIG1,
 						ONENAND_GPMC_CONFIG2,
@@ -110,8 +115,8 @@ void gpmc_init(void)
 						ONENAND_GPMC_CONFIG6,
 						0
 						};
-	u32 base = PISMO1_ONEN_BASE;
-	u32 size = PISMO1_ONEN_SIZE;
+	u32 size = GPMC_SIZE_128M;
+	u32 base = CONFIG_SYS_ONENAND_BASE;
 #else
 	const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
 	u32 size = 0;
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
deleted file mode 100644
index 1832affa5b..0000000000
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *     Manikandan Pillai <mani.pillai@ti.com>
- *
- * Initial Code from:
- *     Richard Woodruff <r-woodruff2@ti.com>
- *     Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-	M_NAND_GPMC_CONFIG1,
-	M_NAND_GPMC_CONFIG2,
-	M_NAND_GPMC_CONFIG3,
-	M_NAND_GPMC_CONFIG4,
-	M_NAND_GPMC_CONFIG5,
-	M_NAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_CMD_ONENAND)
-static const u32 gpmc_onenand[GPMC_MAX_REG] = {
-	ONENAND_GPMC_CONFIG1,
-	ONENAND_GPMC_CONFIG2,
-	ONENAND_GPMC_CONFIG3,
-	ONENAND_GPMC_CONFIG4,
-	ONENAND_GPMC_CONFIG5,
-	ONENAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_ONENAND */
-
-/********************************************************
- *  mem_ok() - test used to see if timings are correct
- *             for a part. Helps in guessing which part
- *             we are currently using.
- *******************************************************/
-u32 mem_ok(u32 cs)
-{
-	u32 val1, val2, addr;
-	u32 pattern = 0x12345678;
-
-	addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
-	writel(0x0, addr + 0x400);	/* clear pos A */
-	writel(pattern, addr);		/* pattern to pos B */
-	writel(0x0, addr + 4);		/* remove pattern off the bus */
-	val1 = readl(addr + 0x400);	/* get pos A value */
-	val2 = readl(addr);		/* get val2 */
-	writel(0x0, addr + 0x400);	/* clear pos A */
-
-	if ((val1 != 0) || (val2 != pattern))	/* see if pos A val changed */
-		return 0;
-	else
-		return 1;
-}
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-			u32 size)
-{
-	writel(0, &cs->config7);
-	sdelay(1000);
-	/* Delay for settling */
-	writel(gpmc_config[0], &cs->config1);
-	writel(gpmc_config[1], &cs->config2);
-	writel(gpmc_config[2], &cs->config3);
-	writel(gpmc_config[3], &cs->config4);
-	writel(gpmc_config[4], &cs->config5);
-	writel(gpmc_config[5], &cs->config6);
-
-	/*
-	 * Enable the config.  size is the CS size and goes in
-	 * bits 11:8.  We set bit 6 to enable this CS and the base
-	 * address goes into bits 5:0.
-	 */
-	 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
-				 ((base >> 24) & GPMC_BASEADDR_MASK),
-				 &cs->config7);
-	sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-	/* putting a blanket check on GPMC based on ZeBu for now */
-	gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
-	const u32 *gpmc_config = NULL;
-	u32 base = 0;
-	u32 size = 0;
-#endif
-	u32 config = 0;
-
-	/* global settings */
-	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
-	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
-	config = readl(&gpmc_cfg->config);
-	config &= (~0xf00);
-	writel(config, &gpmc_cfg->config);
-
-	/*
-	 * Disable the GPMC0 config set by ROM code
-	 * It conflicts with our MPDB (both at 0x08000000)
-	 */
-	writel(0, &gpmc_cfg->cs[0].config7);
-	sdelay(1000);
-
-#if defined(CONFIG_CMD_NAND)	/* CS 0 */
-	gpmc_config = gpmc_m_nand;
-
-	base = PISMO1_NAND_BASE;
-	size = PISMO1_NAND_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-	gpmc_config = gpmc_onenand;
-	base = PISMO1_ONEN_BASE;
-	size = PISMO1_ONEN_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-}
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
new file mode 100644
index 0000000000..bf11a34e54
--- /dev/null
+++ b/arch/arm/cpu/armv7/psci.S
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2013,2014 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension	sec
+
+	.align	5
+	.globl _psci_vectors
+_psci_vectors:
+	b	default_psci_vector	@ reset
+	b	default_psci_vector	@ undef
+	b	_smc_psci		@ smc
+	b	default_psci_vector	@ pabort
+	b	default_psci_vector	@ dabort
+	b	default_psci_vector	@ hyp
+	b	default_psci_vector	@ irq
+	b	psci_fiq_enter		@ fiq
+
+ENTRY(psci_fiq_enter)
+	movs	pc, lr
+ENDPROC(psci_fiq_enter)
+.weak psci_fiq_enter
+
+ENTRY(default_psci_vector)
+	movs	pc, lr
+ENDPROC(default_psci_vector)
+.weak default_psci_vector
+
+ENTRY(psci_cpu_suspend)
+ENTRY(psci_cpu_off)
+ENTRY(psci_cpu_on)
+ENTRY(psci_migrate)
+	mov	r0, #ARM_PSCI_RET_NI	@ Return -1 (Not Implemented)
+	mov	pc, lr
+ENDPROC(psci_migrate)
+ENDPROC(psci_cpu_on)
+ENDPROC(psci_cpu_off)
+ENDPROC(psci_cpu_suspend)
+.weak psci_cpu_suspend
+.weak psci_cpu_off
+.weak psci_cpu_on
+.weak psci_migrate
+
+_psci_table:
+	.word	ARM_PSCI_FN_CPU_SUSPEND
+	.word	psci_cpu_suspend
+	.word	ARM_PSCI_FN_CPU_OFF
+	.word	psci_cpu_off
+	.word	ARM_PSCI_FN_CPU_ON
+	.word	psci_cpu_on
+	.word	ARM_PSCI_FN_MIGRATE
+	.word	psci_migrate
+	.word	0
+	.word	0
+
+_smc_psci:
+	push	{r4-r7,lr}
+
+	@ Switch to secure
+	mrc	p15, 0, r7, c1, c1, 0
+	bic	r4, r7, #1
+	mcr	p15, 0, r4, c1, c1, 0
+	isb
+
+	adr	r4, _psci_table
+1:	ldr	r5, [r4]		@ Load PSCI function ID
+	ldr	r6, [r4, #4]		@ Load target PC
+	cmp	r5, #0			@ If reach the end, bail out
+	moveq	r0, #ARM_PSCI_RET_INVAL	@ Return -2 (Invalid)
+	beq	2f
+	cmp	r0, r5			@ If not matching, try next entry
+	addne	r4, r4, #8
+	bne	1b
+
+	blx	r6			@ Execute PSCI function
+
+	@ Switch back to non-secure
+2:	mcr	p15, 0, r7, c1, c1, 0
+
+	pop	{r4-r7, lr}
+	movs	pc, lr			@ Return to the kernel
+
+	.popsection
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index fad004ca64..dd7de41082 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
index 7a7c97d791..b98137e86a 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -53,6 +53,7 @@ static const struct {
 	{ 0x40, "R8A7740" },
 	{ 0x45, "R8A7790" },
 	{ 0x47, "R8A7791" },
+	{ 0x4C, "R8A7794" },
 	{ 0x0, "CPU" },
 };
 
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
new file mode 100644
index 0000000000..e123663333
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
@@ -0,0 +1,1513 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
+ *     This file is r8a7794 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+
+#define CPU_32_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
+	PORT_1(fn, pfx##31, sfx)
+
+#define CPU_26_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
+
+#define CPU_28_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
+	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
+
+/*
+ * GP_0_0_DATA -> GP_6_25_DATA
+ * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31]
+ *  GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28],
+ *  GP6[29]),GP6[30],GP6[31])
+ */
+#define CPU_ALL_PORT(fn, pfx, sfx)			\
+	CPU_32_PORT(fn, pfx##_0_, sfx),			\
+	CPU_26_PORT(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT(fn, pfx##_2_, sfx),			\
+	CPU_32_PORT(fn, pfx##_3_, sfx),			\
+	CPU_32_PORT(fn, pfx##_4_, sfx),			\
+	CPU_28_PORT(fn, pfx##_5_, sfx),			\
+	CPU_26_PORT(fn, pfx##_6_, sfx)
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
+				       GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
+
+
+#define PORT_10_REV(fn, pfx, sfx)				\
+	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
+	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
+	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
+	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
+	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx)					\
+	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
+	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
+	PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+							  FN_##ipsr, FN_##fn)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
+	FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
+	FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
+	FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
+	FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
+	FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
+	FN_IP2_17_16,
+
+	/* GPSR1 */
+	FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
+	FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
+	FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
+	FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
+	FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
+
+	/* GPSR2 */
+	FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
+	FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
+	FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
+	FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
+	FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
+	FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
+	FN_IP6_5_4, FN_IP6_7_6,
+
+	/* GPSR3 */
+	FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
+	FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
+	FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
+	FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
+	FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
+	FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
+	FN_IP8_22_20,
+
+	/* GPSR4 */
+	FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
+	FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
+	FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
+	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
+	FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
+	FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
+	FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
+
+	/* GPSR5 */
+	FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
+	FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
+	FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
+	FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
+	FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
+	FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
+
+	/* GPSR6 */
+	FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
+	FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
+	FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
+	FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
+	FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	/* IPSR6 */
+	FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
+	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+	FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
+	FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
+	FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
+	FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
+	FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
+	FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
+	FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
+	FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
+	FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
+	FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
+	FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
+	FN_ADIDATA, FN_AD_DI,
+
+	/* IPSR7 */
+	FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
+	FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
+	FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
+	FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
+	FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
+	FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
+	FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
+	FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
+	FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
+	FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
+	FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
+	FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
+	FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
+
+	/* IPSR8 */
+	FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
+	FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
+	FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
+	FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
+	FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+	FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
+	FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
+	FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+	FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
+	FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
+	FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
+	FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
+	FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
+	FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
+	FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+	FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
+	FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
+	FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
+	FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+	FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
+	FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
+	FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
+	FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
+	FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+	FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
+	FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
+	FN_ADICLK_B, FN_AD_CLK_B,
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+
+	/* MOD_SEL */
+	FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+	FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
+	FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
+	FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
+	FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
+	FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
+	FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
+	FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
+	FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
+	FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
+	FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+	FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
+	FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
+	FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
+
+	/* MOD_SEL2 */
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
+	FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
+	FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
+	FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
+	FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
+	FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
+	FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
+	FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
+	FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+	FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
+	FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
+	FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+	FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
+	FN_SEL_RDS_2, FN_SEL_RDS_3,
+
+	/* MOD_SEL3 */
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
+	FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+	FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
+	FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
+	FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
+	FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
+	FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
+	FN_SEL_SSI9_1,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+	A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
+
+	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
+
+	SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
+	SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
+
+	SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
+	SD1_DATA2_MARK, SD1_DATA3_MARK,
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	/* IPSR6 */
+	DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
+	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
+	DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
+	CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
+	AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
+	VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
+	AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
+	VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
+	AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
+	I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
+	VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
+	AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
+	IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
+	I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
+	VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
+	ADIDATA_MARK, AD_DI_MARK,
+
+	/* IPSR7 */
+	ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
+	AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
+	MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
+	AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
+	CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
+	ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
+	AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
+	MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
+	ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
+	SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
+	IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
+	VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
+	SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
+	AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
+	SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
+	DREQ0_N_MARK, SCIFB1_RXD_MARK,
+
+	/* IPSR8 */
+	ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
+	AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
+	I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
+	HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
+	AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
+	SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
+	HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
+	AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
+	HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
+	I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
+	AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
+	SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
+	CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
+	DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
+	I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
+	TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
+	I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
+	FMCLK_C_MARK, RDS_CLK_MARK,
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
+	CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
+	DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
+	SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
+	SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
+	DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
+	SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+	CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
+	DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
+	DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
+	AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
+	MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
+	PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
+	ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
+	PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_DATA(A2_MARK, FN_A2),
+	PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
+	PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
+	PINMUX_DATA(DACK0_MARK, FN_DACK0),
+	PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+	PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
+	PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
+	PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
+	PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
+	PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
+	PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
+	PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
+	PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
+	PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
+	PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
+	PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
+	PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
+	PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
+	PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
+	PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
+	PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
+	PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	/* IPSR6 */
+	PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
+	PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
+	PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
+	PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
+	PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
+	PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
+	PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
+	PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
+	PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
+	PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
+	PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
+	PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
+	PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
+	PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
+	PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
+	PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
+	PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
+	PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
+	PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
+	PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
+	PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
+	PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
+	PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
+	PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
+	PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
+	PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
+	PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
+	PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
+	PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
+	PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
+	PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
+	PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
+	PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
+	PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
+	PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
+
+	/* IPSR7 */
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
+	PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
+	PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
+	PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
+	PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
+	PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
+	PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
+	PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
+	PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
+	PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
+	PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
+	PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
+	PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
+	PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
+
+	/* IPSR8 */
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
+	PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
+	PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
+	PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
+	PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
+	PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
+	PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
+	PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
+	PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
+	PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
+	PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
+	PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
+	PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
+	PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
+	PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
+	PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
+	PINMUX_IPSR_DATA(IP8_19_17, PWM5),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
+	PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
+	PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
+	PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
+	PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
+	PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
+	PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
+	PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
+	PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
+	PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
+	PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
+	PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
+	PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
+	PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
+	PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
+	PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
+	PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
+	PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
+	PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
+	PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
+	PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
+	PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
+	PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
+	PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
+	PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
+	PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
+	PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
+	PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
+	PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
+	PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
+	PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
+	PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
+	PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0),
+	GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
+	GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD),
+	GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2),
+	GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP),
+	GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
+	GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use
+	 */
+
+	/* IPSR6 */
+	GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
+	GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE),
+	GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP),
+	GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB),
+	GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK),
+	GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV),
+	GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2),
+	GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2),
+	GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5),
+	GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5),
+	GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB),
+	GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C),
+	GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA),
+	GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER),
+	GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C),
+	GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N),
+	GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B),
+	GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0),
+	GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK),
+	GPIO_FN(ADIDATA), GPIO_FN(AD_DI),
+
+	/* IPSR7 */
+	GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B),
+	GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP),
+	GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2),
+	GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1),
+	GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3),
+	GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2),
+	GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1),
+	GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D),
+	GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5),
+	GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4),
+	GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6),
+	GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B),
+	GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C),
+	GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B),
+	GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C),
+	GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B),
+	GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B),
+	GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0),
+	GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E),
+	GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N),
+	GPIO_FN(SCIFB1_RXD),
+
+	/* IPSR8 */
+	GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B),
+	GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B),
+	GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C),
+	GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B),
+	GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C),
+	GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B),
+	GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D),
+	GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B),
+	GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D),
+	GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B),
+	GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS),
+	GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C),
+	GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK),
+	GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA),
+	GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK),
+	GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL),
+	GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0),
+	GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B),
+	GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5),
+	GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D),
+	GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD),
+	GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B),
+	GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK),
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C),
+	GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5),
+	GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1),
+	GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B),
+	GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13),
+	GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C),
+	GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14),
+	GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C),
+	GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15),
+	GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C),
+	GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B),
+	GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7),
+	GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D),
+	GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129),
+	GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B),
+	GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129),
+	GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B),
+	GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B),
+	GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B),
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP2_17_16,
+		GP_0_30_FN, FN_IP2_15_14,
+		GP_0_29_FN, FN_IP2_13_12,
+		GP_0_28_FN, FN_IP2_11_10,
+		GP_0_27_FN, FN_IP2_9_8,
+		GP_0_26_FN, FN_IP2_7_6,
+		GP_0_25_FN, FN_IP2_5_4,
+		GP_0_24_FN, FN_IP2_3_2,
+		GP_0_23_FN, FN_IP2_1_0,
+		GP_0_22_FN, FN_IP1_31_30,
+		GP_0_21_FN, FN_IP1_29_28,
+		GP_0_20_FN, FN_IP1_27,
+		GP_0_19_FN, FN_IP1_26,
+		GP_0_18_FN, FN_A2,
+		GP_0_17_FN, FN_IP1_24,
+		GP_0_16_FN, FN_IP1_23_22,
+		GP_0_15_FN, FN_IP1_21_20,
+		GP_0_14_FN, FN_IP1_19_18,
+		GP_0_13_FN, FN_IP1_17_15,
+		GP_0_12_FN, FN_IP1_14_13,
+		GP_0_11_FN, FN_IP1_12_11,
+		GP_0_10_FN, FN_IP1_10_8,
+		GP_0_9_FN, FN_IP1_7_6,
+		GP_0_8_FN, FN_IP1_5_4,
+		GP_0_7_FN, FN_IP1_3_2,
+		GP_0_6_FN, FN_IP1_1_0,
+		GP_0_5_FN, FN_IP0_31_30,
+		GP_0_4_FN, FN_IP0_29_28,
+		GP_0_3_FN, FN_IP0_27_26,
+		GP_0_2_FN, FN_IP0_25,
+		GP_0_1_FN, FN_IP0_24,
+		GP_0_0_FN, FN_IP0_23_22, }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_FN, FN_DACK0,
+		GP_1_24_FN, FN_IP7_31,
+		GP_1_23_FN, FN_IP4_1_0,
+		GP_1_22_FN, FN_WE1_N,
+		GP_1_21_FN, FN_WE0_N,
+		GP_1_20_FN, FN_IP3_31,
+		GP_1_19_FN, FN_IP3_30,
+		GP_1_18_FN, FN_IP3_29_27,
+		GP_1_17_FN, FN_IP3_26_24,
+		GP_1_16_FN, FN_IP3_23_21,
+		GP_1_15_FN, FN_IP3_20_18,
+		GP_1_14_FN, FN_IP3_17_15,
+		GP_1_13_FN, FN_IP3_14_13,
+		GP_1_12_FN, FN_IP3_12,
+		GP_1_11_FN, FN_IP3_11,
+		GP_1_10_FN, FN_IP3_10,
+		GP_1_9_FN, FN_IP3_9_8,
+		GP_1_8_FN, FN_IP3_7_6,
+		GP_1_7_FN, FN_IP3_5_4,
+		GP_1_6_FN, FN_IP3_3_2,
+		GP_1_5_FN, FN_IP3_1_0,
+		GP_1_4_FN, FN_IP2_31_30,
+		GP_1_3_FN, FN_IP2_29_27,
+		GP_1_2_FN, FN_IP2_26_24,
+		GP_1_1_FN, FN_IP2_23_21,
+		GP_1_0_FN, FN_IP2_20_18, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		GP_2_31_FN, FN_IP6_7_6,
+		GP_2_30_FN, FN_IP6_5_4,
+		GP_2_29_FN, FN_IP6_3_2,
+		GP_2_28_FN, FN_IP6_1_0,
+		GP_2_27_FN, FN_IP5_31_30,
+		GP_2_26_FN, FN_IP5_29_28,
+		GP_2_25_FN, FN_IP5_27_26,
+		GP_2_24_FN, FN_IP5_25_24,
+		GP_2_23_FN, FN_IP5_23_22,
+		GP_2_22_FN, FN_IP5_21_20,
+		GP_2_21_FN, FN_IP5_19_18,
+		GP_2_20_FN, FN_IP5_17_16,
+		GP_2_19_FN, FN_IP5_15_14,
+		GP_2_18_FN, FN_IP5_13_12,
+		GP_2_17_FN, FN_IP5_11_9,
+		GP_2_16_FN, FN_IP5_8_6,
+		GP_2_15_FN, FN_IP5_5_4,
+		GP_2_14_FN, FN_IP5_3_2,
+		GP_2_13_FN, FN_IP5_1_0,
+		GP_2_12_FN, FN_IP4_31_30,
+		GP_2_11_FN, FN_IP4_29_28,
+		GP_2_10_FN, FN_IP4_27_26,
+		GP_2_9_FN, FN_IP4_25_23,
+		GP_2_8_FN, FN_IP4_22_20,
+		GP_2_7_FN, FN_IP4_19_18,
+		GP_2_6_FN, FN_IP4_17_16,
+		GP_2_5_FN, FN_IP4_15_14,
+		GP_2_4_FN, FN_IP4_13_12,
+		GP_2_3_FN, FN_IP4_11_10,
+		GP_2_2_FN, FN_IP4_9_8,
+		GP_2_1_FN, FN_IP4_7_5,
+		GP_2_0_FN, FN_IP4_4_2 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP8_22_20,
+		GP_3_30_FN, FN_IP8_19_17,
+		GP_3_29_FN, FN_IP8_16_15,
+		GP_3_28_FN, FN_IP8_14_12,
+		GP_3_27_FN, FN_IP8_11_9,
+		GP_3_26_FN, FN_IP8_8_6,
+		GP_3_25_FN, FN_IP8_5_3,
+		GP_3_24_FN, FN_IP8_2_0,
+		GP_3_23_FN, FN_IP7_29_27,
+		GP_3_22_FN, FN_IP7_26_24,
+		GP_3_21_FN, FN_IP7_23_21,
+		GP_3_20_FN, FN_IP7_20_18,
+		GP_3_19_FN, FN_IP7_17_15,
+		GP_3_18_FN, FN_IP7_14_12,
+		GP_3_17_FN, FN_IP7_11_9,
+		GP_3_16_FN, FN_IP7_8_6,
+		GP_3_15_FN, FN_IP7_5_3,
+		GP_3_14_FN, FN_IP7_2_0,
+		GP_3_13_FN, FN_IP6_31_29,
+		GP_3_12_FN, FN_IP6_28_26,
+		GP_3_11_FN, FN_IP6_25_23,
+		GP_3_10_FN, FN_IP6_22_20,
+		GP_3_9_FN, FN_IP6_19_17,
+		GP_3_8_FN, FN_IP6_16,
+		GP_3_7_FN, FN_IP6_15,
+		GP_3_6_FN, FN_IP6_14,
+		GP_3_5_FN, FN_IP6_13,
+		GP_3_4_FN, FN_IP6_12,
+		GP_3_3_FN, FN_IP6_11,
+		GP_3_2_FN, FN_IP6_10,
+		GP_3_1_FN, FN_IP6_9,
+		GP_3_0_FN, FN_IP6_8 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP11_17_16,
+		GP_4_30_FN, FN_IP11_15_14,
+		GP_4_29_FN, FN_IP11_13_11,
+		GP_4_28_FN, FN_IP11_10_8,
+		GP_4_27_FN, FN_IP11_7_6,
+		GP_4_26_FN, FN_IP11_5_3,
+		GP_4_25_FN, FN_IP11_2_0,
+		GP_4_24_FN, FN_IP10_31_30,
+		GP_4_23_FN, FN_IP10_29_27,
+		GP_4_22_FN, FN_IP10_26_24,
+		GP_4_21_FN, FN_IP10_23_21,
+		GP_4_20_FN, FN_IP10_20_18,
+		GP_4_19_FN, FN_IP10_17_15,
+		GP_4_18_FN, FN_IP10_14_12,
+		GP_4_17_FN, FN_IP10_11_9,
+		GP_4_16_FN, FN_IP10_8_6,
+		GP_4_15_FN, FN_IP10_5_3,
+		GP_4_14_FN, FN_IP10_2_0,
+		GP_4_13_FN, FN_IP9_30_28,
+		GP_4_12_FN, FN_IP9_27_25,
+		GP_4_11_FN, FN_IP9_24_22,
+		GP_4_10_FN, FN_IP9_21_19,
+		GP_4_9_FN, FN_IP9_18_17,
+		GP_4_8_FN, FN_IP9_16_15,
+		GP_4_7_FN, FN_IP9_14_12,
+		GP_4_6_FN, FN_IP9_11_9,
+		GP_4_5_FN, FN_IP9_8_6,
+		GP_4_4_FN, FN_IP9_5_3,
+		GP_4_3_FN, FN_IP9_2_0,
+		GP_4_2_FN, FN_IP8_31_29,
+		GP_4_1_FN, FN_IP8_28_26,
+		GP_4_0_FN, FN_IP8_25_23 }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_27_FN, FN_USB1_OVC,
+		GP_5_26_FN, FN_USB1_PWEN,
+		GP_5_25_FN, FN_USB0_OVC,
+		GP_5_24_FN, FN_USB0_PWEN,
+		GP_5_23_FN, FN_IP13_26_24,
+		GP_5_22_FN, FN_IP13_23_21,
+		GP_5_21_FN, FN_IP13_20_18,
+		GP_5_20_FN, FN_IP13_17_15,
+		GP_5_19_FN, FN_IP13_14_12,
+		GP_5_18_FN, FN_IP13_11_9,
+		GP_5_17_FN, FN_IP13_8_6,
+		GP_5_16_FN, FN_IP13_5_3,
+		GP_5_15_FN, FN_IP13_2_0,
+		GP_5_14_FN, FN_IP12_29_27,
+		GP_5_13_FN, FN_IP12_26_24,
+		GP_5_12_FN, FN_IP12_23_21,
+		GP_5_11_FN, FN_IP12_20_18,
+		GP_5_10_FN, FN_IP12_17_15,
+		GP_5_9_FN, FN_IP12_14_13,
+		GP_5_8_FN, FN_IP12_12_11,
+		GP_5_7_FN, FN_IP12_10_9,
+		GP_5_6_FN, FN_IP12_8_6,
+		GP_5_5_FN, FN_IP12_5_3,
+		GP_5_4_FN, FN_IP12_2_0,
+		GP_5_3_FN, FN_IP11_29_27,
+		GP_5_2_FN, FN_IP11_26_24,
+		GP_5_1_FN, FN_IP11_23_21,
+		GP_5_0_FN, FN_IP11_20_18 }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_25_FN, FN_IP0_21_20,
+		GP_6_24_FN, FN_IP0_19_18,
+		GP_6_23_FN, FN_IP0_17,
+		GP_6_22_FN, FN_IP0_16,
+		GP_6_21_FN, FN_IP0_15,
+		GP_6_20_FN, FN_IP0_14,
+		GP_6_19_FN, FN_IP0_13,
+		GP_6_18_FN, FN_IP0_12,
+		GP_6_17_FN, FN_IP0_11,
+		GP_6_16_FN, FN_IP0_10,
+		GP_6_15_FN, FN_IP0_9_8,
+		GP_6_14_FN, FN_IP0_0,
+		GP_6_13_FN, FN_SD1_DATA3,
+		GP_6_12_FN, FN_SD1_DATA2,
+		GP_6_11_FN, FN_SD1_DATA1,
+		GP_6_10_FN, FN_SD1_DATA0,
+		GP_6_9_FN, FN_SD1_CMD,
+		GP_6_8_FN, FN_SD1_CLK,
+		GP_6_7_FN, FN_SD0_WP,
+		GP_6_6_FN, FN_SD0_CD,
+		GP_6_5_FN, FN_SD0_DATA3,
+		GP_6_4_FN, FN_SD0_DATA2,
+		GP_6_3_FN, FN_SD0_DATA1,
+		GP_6_2_FN, FN_SD0_DATA0,
+		GP_6_1_FN, FN_SD0_CMD,
+		GP_6_0_FN, FN_SD0_CLK }
+	},
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+			     3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+			     2, 2) {
+		/* IP6_31_29 [3] */
+		FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
+		FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
+		/* IP6_28_26 [3] */
+		FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
+		FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
+		/* IP6_25_23 [3] */
+		FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
+		FN_AVB_COL, 0, 0, 0,
+		/* IP6_22_20 [3] */
+		FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
+		FN_AVB_RX_ER, 0, 0, 0,
+		/* IP6_19_17 [3] */
+		FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
+		FN_AVB_RXD7, 0, 0, 0,
+		/* IP6_16 [1] */
+		FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+		/* IP6_15 [1] */
+		FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
+		/* IP6_14 [1] */
+		FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
+		/* IP6_13 [1] */
+		FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
+		/* IP6_12 [1] */
+		FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
+		/* IP6_11 [1] */
+		FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
+		/* IP6_10 [1] */
+		FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
+		/* IP6_9 [1] */
+		FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
+		/* IP6_8 [1] */
+		FN_VI0_CLK, FN_AVB_RX_CLK,
+		/* IP6_7_6 [2] */
+		FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
+		/* IP6_5_4 [2] */
+		FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
+		/* IP6_3_2 [2] */
+		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+		/* IP6_1_0 [2] */
+		FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+			     1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+		/* IP7_31 [1] */
+		FN_DREQ0_N, FN_SCIFB1_RXD,
+		/* IP7_30 [1] */
+		0, 0,
+		/* IP7_29_27 [3] */
+		FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
+		FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
+		/* IP7_26_24 [3] */
+		FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
+		FN_SSI_SCK6_B, 0, 0, 0,
+		/* IP7_23_21 [3] */
+		FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
+		FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
+		/* IP7_20_18 [3] */
+		FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
+		FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
+		/* IP7_17_15 [3] */
+		FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
+		FN_SSI_SCK5_B, 0, 0, 0,
+		/* IP7_14_12 [3] */
+		FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
+		FN_AVB_TXD4, FN_ADICHS2, 0, 0,
+		/* IP7_11_9 [3] */
+		FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
+		FN_AVB_TXD3, FN_ADICHS1, 0, 0,
+		/* IP7_8_6 [3] */
+		FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
+		FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
+		/* IP7_5_3 [3] */
+		FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
+		FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
+		/* IP7_2_0 [3] */
+		FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
+		FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+			     3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
+		/* IP8_31_29 [3] */
+		FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
+		FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+		/* IP8_28_26 [3] */
+		FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
+		FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
+		/* IP8_25_23 [3] */
+		FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
+		FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
+		/* IP8_22_20 [3] */
+		FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
+		FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
+		/* IP8_19_17 [3] */
+		FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
+		FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
+		/* IP8_16_15 [2] */
+		FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+		/* IP8_14_12 [3] */
+		FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
+		FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
+		/* IP8_11_9 [3] */
+		FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+		FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
+		/* IP8_8_6 [3] */
+		FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
+		FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
+		/* IP8_5_3 [3] */
+		FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
+		FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
+		/* IP8_2_0 [3] */
+		FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
+		FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
+	},
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+			     2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
+		/* IP11_31_30 [2] */
+		0, 0, 0, 0,
+		/* IP11_29_27 [3] */
+		FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
+		FN_AD_CLK_B, 0, 0, 0,
+		/* IP11_26_24 [3] */
+		FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
+		FN_AD_DO_B, 0, 0, 0,
+		/* IP11_23_21 [3] */
+		FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+		FN_AD_DI_B, FN_PCMWE_N, 0, 0,
+		/* IP11_20_18 [3] */
+		FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
+		FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
+		/* IP11_17_16 [2] */
+		FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
+		/* IP11_15_14 [2] */
+		FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
+		/* IP11_13_11 [3] */
+		FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+		FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
+		/* IP11_10_8 [3] */
+		FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
+		FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
+		/* IP11_7_6 [2] */
+		FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
+		FN_CAN_DEBUGOUT13,
+		/* IP11_5_3 [3] */
+		FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+		FN_CAN_DEBUGOUT12, 0, 0, 0,
+		/* IP11_2_0 [3] */
+		FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+		FN_CAN_DEBUGOUT11, 0, 0, 0, }
+	},
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+
+	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+			     2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
+			     2, 1) {
+		/* SEL_ADG [2] */
+		FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+		/* SEL_ADI [1] */
+		FN_SEL_ADI_0, FN_SEL_ADI_1,
+		/* SEL_CAN [2] */
+		FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+		/* SEL_DARC [3] */
+		FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
+		FN_SEL_DARC_4, 0, 0, 0,
+		/* SEL_DR0 [1] */
+		FN_SEL_DR0_0, FN_SEL_DR0_1,
+		/* SEL_DR1 [1] */
+		FN_SEL_DR1_0, FN_SEL_DR1_1,
+		/* SEL_DR2 [1] */
+		FN_SEL_DR2_0, FN_SEL_DR2_1,
+		/* SEL_DR3 [1] */
+		FN_SEL_DR3_0, FN_SEL_DR3_1,
+		/* SEL_ETH [1] */
+		FN_SEL_ETH_0, FN_SEL_ETH_1,
+		/* SLE_FSN [1] */
+		FN_SEL_FSN_0, FN_SEL_FSN_1,
+		/* SEL_IC200 [3] */
+		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
+		FN_SEL_I2C00_4, 0, 0, 0,
+		/* SEL_I2C01 [3] */
+		FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
+		FN_SEL_I2C01_4, 0, 0, 0,
+		/* SEL_I2C02 [3] */
+		FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+		FN_SEL_I2C02_4, 0, 0, 0,
+		/* SEL_I2C03 [3] */
+		FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+		FN_SEL_I2C03_4, 0, 0, 0,
+		/* SEL_I2C04 [3] */
+		FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
+		FN_SEL_I2C04_4, 0, 0, 0,
+		/* SEL_IIC00 [2] */
+		FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
+		/* SEL_AVB [1] */
+		FN_SEL_AVB_0, FN_SEL_AVB_1, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+			     2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
+			     2, 2, 2, 1, 1, 2) {
+		/* SEL_IEB [2] */
+		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+		/* SEL_IIC0 [2] */
+		FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
+		/* SEL_LBS [1] */
+		FN_SEL_LBS_0, FN_SEL_LBS_1,
+		/* SEL_MSI1 [1] */
+		FN_SEL_MSI1_0, FN_SEL_MSI1_1,
+		/* SEL_MSI2 [1] */
+		FN_SEL_MSI2_0, FN_SEL_MSI2_1,
+		/* SEL_RAD [1] */
+		FN_SEL_RAD_0, FN_SEL_RAD_1,
+		/* SEL_RCN [1] */
+		FN_SEL_RCN_0, FN_SEL_RCN_1,
+		/* SEL_RSP [1] */
+		FN_SEL_RSP_0, FN_SEL_RSP_1,
+		/* SEL_SCIFA0 [2] */
+		FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
+		FN_SEL_SCIFA0_3,
+		/* SEL_SCIFA1 [2] */
+		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+		/* SEL_SCIFA2 [1] */
+		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+		/* SEL_SCIFA3 [1] */
+		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+		/* SEL_SCIFA4 [2] */
+		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+		FN_SEL_SCIFA4_3,
+		/* SEL_SCIFA5 [2] */
+		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+		FN_SEL_SCIFA5_3,
+		/* SEL_SPDM [1] */
+		FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+		/* SEL_TMU [1] */
+		FN_SEL_TMU_0, FN_SEL_TMU_1,
+		/* SEL_TSIF0 [2] */
+		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+		/* SEL_CAN0 [2] */
+		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+		/* SEL_CAN1 [2] */
+		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+		/* SEL_HSCIF0 [1] */
+		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+		/* SEL_HSCIF1 [1] */
+		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+		/* SEL_RDS [2] */
+		FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+			     2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+		/* SEL_SCIF0 [2] */
+		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+		/* SEL_SCIF1 [2] */
+		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
+		/* SEL_SCIF2 [2] */
+		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
+		/* SEL_SCIF3 [1] */
+		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+		/* SEL_SCIF4 [3] */
+		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+		FN_SEL_SCIF4_4, 0, 0, 0,
+		/* SEL_SCIF5 [2] */
+		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
+		/* SEL_SSI1 [1] */
+		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+		/* SEL_SSI2 [1] */
+		FN_SEL_SSI2_0, FN_SEL_SSI2_1,
+		/* SEL_SSI4 [1] */
+		FN_SEL_SSI4_0, FN_SEL_SSI4_1,
+		/* SEL_SSI5 [1] */
+		FN_SEL_SSI5_0, FN_SEL_SSI5_1,
+		/* SEL_SSI6 [1] */
+		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+		/* SEL_SSI7 [1] */
+		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+		/* SEL_SSI8 [1] */
+		FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+		/* SEL_SSI9 [1] */
+		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_27_IN, GP_5_27_OUT,
+		GP_5_26_IN, GP_5_26_OUT,
+		GP_5_25_IN, GP_5_25_OUT,
+		GP_5_24_IN, GP_5_24_OUT,
+		GP_5_23_IN, GP_5_23_OUT,
+		GP_5_22_IN, GP_5_22_OUT,
+		GP_5_21_IN, GP_5_21_OUT,
+		GP_5_20_IN, GP_5_20_OUT,
+		GP_5_19_IN, GP_5_19_OUT,
+		GP_5_18_IN, GP_5_18_OUT,
+		GP_5_17_IN, GP_5_17_OUT,
+		GP_5_16_IN, GP_5_16_OUT,
+		GP_5_15_IN, GP_5_15_OUT,
+		GP_5_14_IN, GP_5_14_OUT,
+		GP_5_13_IN, GP_5_13_OUT,
+		GP_5_12_IN, GP_5_12_OUT,
+		GP_5_11_IN, GP_5_11_OUT,
+		GP_5_10_IN, GP_5_10_OUT,
+		GP_5_9_IN, GP_5_9_OUT,
+		GP_5_8_IN, GP_5_8_OUT,
+		GP_5_7_IN, GP_5_7_OUT,
+		GP_5_6_IN, GP_5_6_OUT,
+		GP_5_5_IN, GP_5_5_OUT,
+		GP_5_4_IN, GP_5_4_OUT,
+		GP_5_3_IN, GP_5_3_OUT,
+		GP_5_2_IN, GP_5_2_OUT,
+		GP_5_1_IN, GP_5_1_OUT,
+		GP_5_0_IN, GP_5_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_25_IN, GP_6_25_OUT,
+		GP_6_24_IN, GP_6_24_OUT,
+		GP_6_23_IN, GP_6_23_OUT,
+		GP_6_22_IN, GP_6_22_OUT,
+		GP_6_21_IN, GP_6_21_OUT,
+		GP_6_20_IN, GP_6_20_OUT,
+		GP_6_19_IN, GP_6_19_OUT,
+		GP_6_18_IN, GP_6_18_OUT,
+		GP_6_17_IN, GP_6_17_OUT,
+		GP_6_16_IN, GP_6_16_OUT,
+		GP_6_15_IN, GP_6_15_OUT,
+		GP_6_14_IN, GP_6_14_OUT,
+		GP_6_13_IN, GP_6_13_OUT,
+		GP_6_12_IN, GP_6_12_OUT,
+		GP_6_11_IN, GP_6_11_OUT,
+		GP_6_10_IN, GP_6_10_OUT,
+		GP_6_9_IN, GP_6_9_OUT,
+		GP_6_8_IN, GP_6_8_OUT,
+		GP_6_7_IN, GP_6_7_OUT,
+		GP_6_6_IN, GP_6_6_OUT,
+		GP_6_5_IN, GP_6_5_OUT,
+		GP_6_4_IN, GP_6_4_OUT,
+		GP_6_3_IN, GP_6_3_OUT,
+		GP_6_2_IN, GP_6_2_OUT,
+		GP_6_1_IN, GP_6_1_OUT,
+		GP_6_0_IN, GP_6_0_OUT, }
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
+		0, 0, 0, 0,
+		GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA,
+		GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
+		GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
+		GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
+		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
+		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
+		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_6_25_DATA, GP_6_24_DATA,
+		GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA,
+		GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA,
+		GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
+		GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
+		GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
+		GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
+	},
+	{ },
+};
+
+static struct pinmux_info r8a7794_pinmux_info = {
+	.name = "r8a7794_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_AD_CLK_B,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7794_pinmux_init(void)
+{
+	register_pinmux(&r8a7794_pinmux_info);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index a64bfa18e0..6c706393d3 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,8 @@ obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
+obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
+obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
 
 ifndef CONFIG_SPL_BUILD
@@ -18,6 +20,8 @@ obj-y	+= cpu_info.o
 endif
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SUN4I)	+= dram.o
+obj-$(CONFIG_SUN5I)	+= dram.o
 obj-$(CONFIG_SUN7I)	+= dram.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 49c94489ee..8f2cef332f 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -11,6 +11,7 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <serial.h>
@@ -24,6 +25,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/timer.h>
 
+#include <linux/compiler.h>
+
 #ifdef CONFIG_SPL_BUILD
 /* Pointer to the global data structure for SPL */
 DECLARE_GLOBAL_DATA_PTR;
@@ -47,15 +50,38 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
+#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+#else
+#error Unsupported console port number. Please fix pin mux settings in board.c
+#endif
 
 	return 0;
 }
 
 void reset_cpu(ulong addr)
 {
+	static const struct sunxi_wdog *wdog =
+		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+	/* Set the watchdog for its shortest interval (.5s) and wait */
+	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+
+	while (1) {
+		/* sun5i sometimes gets stuck without this */
+		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+	}
 }
 
 /* do some early init */
@@ -72,11 +98,16 @@ void s_init(void)
 	clock_init();
 	timer_init();
 	gpio_init();
+	i2c_init_board();
 
 #ifdef CONFIG_SPL_BUILD
 	gd = &gdata;
 	preloader_console_init();
 
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	/* Needed early by sunxi_board_init if PMU is enabled */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
 	sunxi_board_init();
 #endif
 }
@@ -96,7 +127,15 @@ void enable_caches(void)
  */
 int cpu_eth_init(bd_t *bis)
 {
-	int rc;
+	__maybe_unused int rc;
+
+#ifdef CONFIG_SUNXI_EMAC
+	rc = sunxi_emac_initialize(bis);
+	if (rc < 0) {
+		printf("sunxi: failed to initialize emac\n");
+		return rc;
+	}
+#endif
 
 #ifdef CONFIG_SUNXI_GMAC
 	rc = sunxi_gmac_initialize(bis);
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 5a7da3c6bf..b8b16cff95 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -36,8 +36,7 @@ void clock_init_safe(void)
 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
 #ifdef CONFIG_SUN7I
-	writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
-	       &ccm->ahb_gate0);
+	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 }
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index b4c3d5c6dd..5cf35acc1e 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -13,7 +13,22 @@
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
+#ifdef CONFIG_SUN4I
+	puts("CPU:   Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_SUN5I
+	u32 val = readl(SUNXI_SID_BASE + 0x08);
+	switch ((val >> 12) & 0xf) {
+	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
+	case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
+	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
+	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
+	}
+#elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
+#else
+#warning Please update cpu_info.c with correct CPU information
+	puts("CPU:   SUNXI Family\n");
+#endif
 	return 0;
 }
 #endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index b43c4b41d3..0f1ceecc1d 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -53,16 +53,37 @@ static void mctl_ddr3_reset(void)
 	struct sunxi_dram_reg *dram =
 			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
-	clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-	udelay(2);
-	setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#ifdef CONFIG_SUN4I
+	struct sunxi_timer_reg *timer =
+			(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+	u32 reg_val;
+
+	writel(0, &timer->cpu_cfg);
+	reg_val = readl(&timer->cpu_cfg);
+
+	if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
+	    CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+		udelay(2);
+		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+	} else
+#endif
+	{
+		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+		udelay(2);
+		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+	}
 }
 
 static void mctl_set_drive(void)
 {
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
+#ifdef CONFIG_SUN7I
 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+#else
+	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
+#endif
 			DRAM_MCR_MODE_EN(0x3) |
 			0xffc);
 }
@@ -134,6 +155,26 @@ static void mctl_enable_dllx(u32 phase)
 }
 
 static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN5I
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0x1031, 0x1031, 0x0735, 0x1035,
+	0x1035, 0x0731, 0x1031, 0,
+	0x0301, 0x0301, 0x0301, 0x0301,
+	0x0301, 0x0301, 0x0301, 0
+#endif
+#ifdef CONFIG_SUN4I
+	0x0301, 0x0301, 0x0301, 0x0301,
+	0x0301, 0x0301, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0x1031, 0x1031, 0x0735, 0x5031,
+	0x1035, 0x0731, 0x1031, 0x0735,
+	0x1035, 0x1031, 0x0731, 0x1035,
+	0x1031, 0x0301, 0x0301, 0x0731
+#endif
 #ifdef CONFIG_SUN7I
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0x0301, 0x0301,
@@ -223,22 +264,38 @@ static void mctl_setup_dram_clock(u32 clk)
 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
 #endif
 
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	/* setup MBUS clock */
 	reg_val = CCM_MBUS_CTRL_GATE |
+#ifdef CONFIG_SUN7I
 		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
 		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
 		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#else /* defined(CONFIG_SUN5I) */
+		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#endif
 	writel(reg_val, &ccm->mbus_clk_cfg);
+#endif
 
 	/*
 	 * open DRAMC AHB & DLL register clock
 	 * close it first
 	 */
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
 	udelay(22);
 
 	/* then open it */
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
 	udelay(22);
 }
 
@@ -385,6 +442,13 @@ static void dramc_clock_output_en(u32 on)
 	else
 		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
 #endif
+#ifdef CONFIG_SUN4I
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	if (on)
+		setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+	else
+		clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+#endif
 }
 
 static const u16 tRFC_table[2][6] = {
@@ -420,12 +484,25 @@ unsigned long dramc_init(struct dram_para *para)
 	/* setup DRAM relative clock */
 	mctl_setup_dram_clock(para->clock);
 
+#ifdef CONFIG_SUN5I
+	/* Disable any pad power save control */
+	writel(0, &dram->ppwrsctl);
+#endif
+
 	/* reset external DRAM */
+#ifndef CONFIG_SUN7I
+	mctl_ddr3_reset();
+#endif
 	mctl_set_drive();
 
 	/* dram clock off */
 	dramc_clock_output_en(0);
 
+#ifdef CONFIG_SUN4I
+	/* select dram controller 1 */
+	writel(DRAM_CSEL_MAGIC, &dram->csel);
+#endif
+
 	mctl_itm_disable();
 	mctl_enable_dll0(para->tpr3);
 
@@ -482,6 +559,9 @@ unsigned long dramc_init(struct dram_para *para)
 		mctl_ddr3_reset();
 	else
 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#else
+	/* dram clock on */
+	dramc_clock_output_en(1);
 #endif
 
 	udelay(1);
@@ -490,6 +570,22 @@ unsigned long dramc_init(struct dram_para *para)
 
 	mctl_enable_dllx(para->tpr3);
 
+#ifdef CONFIG_SUN4I
+	/* set odt impedance divide ratio */
+	reg_val = ((para->zq) >> 8) & 0xfffff;
+	reg_val |= ((para->zq) & 0xff) << 20;
+	reg_val |= (para->zq) & 0xf0000000;
+	writel(reg_val, &dram->zqcr0);
+#endif
+
+#ifdef CONFIG_SUN4I
+	/* set I/O configure register */
+	reg_val = 0x00cc0000;
+	reg_val |= (para->odt_en) & 0x3;
+	reg_val |= ((para->odt_en) & 0x3) << 30;
+	writel(reg_val, &dram->iocr);
+#endif
+
 	/* set refresh period */
 	dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
 
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
index 364e35c32f..928b7c19e0 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
@@ -27,6 +27,11 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
 	. = .;
 
 	. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
index 5008028aae..53f0cbd2b7 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
@@ -27,6 +27,7 @@ SECTIONS
 	.text      :
 	{
 		__start = .;
+		*(.vectors)
 		arch/arm/cpu/armv7/start.o	(.text)
 		*(.text*)
 	} > .sram
@@ -38,6 +39,11 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .sram
+
+	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
new file mode 100644
index 0000000000..0b0d6a76fc
--- /dev/null
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <asm/global_data.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+static int fdt_psci(void *fdt)
+{
+#ifdef CONFIG_ARMV7_PSCI
+	int nodeoff;
+	int tmp;
+
+	nodeoff = fdt_path_offset(fdt, "/cpus");
+	if (nodeoff < 0) {
+		printf("couldn't find /cpus\n");
+		return nodeoff;
+	}
+
+	/* add 'enable-method = "psci"' to each cpu node */
+	for (tmp = fdt_first_subnode(fdt, nodeoff);
+	     tmp >= 0;
+	     tmp = fdt_next_subnode(fdt, tmp)) {
+		const struct fdt_property *prop;
+		int len;
+
+		prop = fdt_get_property(fdt, tmp, "device_type", &len);
+		if (!prop)
+			continue;
+		if (len < 4)
+			continue;
+		if (strcmp(prop->data, "cpu"))
+			continue;
+
+		fdt_setprop_string(fdt, tmp, "enable-method", "psci");
+	}
+
+	nodeoff = fdt_path_offset(fdt, "/psci");
+	if (nodeoff < 0) {
+		nodeoff = fdt_path_offset(fdt, "/");
+		if (nodeoff < 0)
+			return nodeoff;
+
+		nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
+		if (nodeoff < 0)
+			return nodeoff;
+	}
+
+	tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
+	if (tmp)
+		return tmp;
+#endif
+	return 0;
+}
+
+int armv7_update_dt(void *fdt)
+{
+#ifndef CONFIG_ARMV7_SECURE_BASE
+	/* secure code lives in RAM, keep it alive */
+	fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+			__secure_end - __secure_start);
+#endif
+
+	return fdt_psci(fdt);
+}
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 2cd604f97f..651ca4015d 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -13,17 +13,10 @@
 #include <asm/armv7.h>
 #include <asm/gic.h>
 #include <asm/io.h>
+#include <asm/secure.h>
 
 unsigned long gic_dist_addr;
 
-static unsigned int read_cpsr(void)
-{
-	unsigned int reg;
-
-	asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
-	return reg;
-}
-
 static unsigned int read_id_pfr1(void)
 {
 	unsigned int reg;
@@ -37,25 +30,8 @@ static unsigned long get_gicd_base_address(void)
 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
 	return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
 #else
-	unsigned midr;
 	unsigned periphbase;
 
-	/* check whether we are an Cortex-A15 or A7.
-	 * The actual HYP switch should work with all CPUs supporting
-	 * the virtualization extension, but we need the GIC address,
-	 * which we know only for sure for those two CPUs.
-	 */
-	asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
-	switch (midr & MIDR_PRIMARY_PART_MASK) {
-	case MIDR_CORTEX_A9_R0P1:
-	case MIDR_CORTEX_A15_R0P0:
-	case MIDR_CORTEX_A7_R0P0:
-		break;
-	default:
-		printf("nonsec: could not determine GIC address.\n");
-		return -1;
-	}
-
 	/* get the GIC base address from the CBAR register */
 	asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
 
@@ -72,6 +48,18 @@ static unsigned long get_gicd_base_address(void)
 #endif
 }
 
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV7_SECURE_BASE
+	size_t sz = __secure_end - __secure_start;
+
+	memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
+	flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
+			   CONFIG_ARMV7_SECURE_BASE + sz + 1);
+	invalidate_icache_all();
+#endif
+}
+
 static void kick_secondary_cpus_gic(unsigned long gicdaddr)
 {
 	/* kick all CPUs (except this one) by writing to GICD_SGIR */
@@ -83,35 +71,7 @@ void __weak smp_kick_all_cpus(void)
 	kick_secondary_cpus_gic(gic_dist_addr);
 }
 
-int armv7_switch_hyp(void)
-{
-	unsigned int reg;
-
-	/* check whether we are in HYP mode already */
-	if ((read_cpsr() & 0x1f) == 0x1a) {
-		debug("CPU already in HYP mode\n");
-		return 0;
-	}
-
-	/* check whether the CPU supports the virtualization extensions */
-	reg = read_id_pfr1();
-	if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
-		printf("HYP mode: Virtualization extensions not implemented.\n");
-		return -1;
-	}
-
-	/* call the HYP switching code on this CPU also */
-	_switch_to_hyp();
-
-	if ((read_cpsr() & 0x1F) != 0x1a) {
-		printf("HYP mode: switch not successful.\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-int armv7_switch_nonsec(void)
+int armv7_init_nonsec(void)
 {
 	unsigned int reg;
 	unsigned itlinesnr, i;
@@ -147,11 +107,13 @@ int armv7_switch_nonsec(void)
 	for (i = 1; i <= itlinesnr; i++)
 		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
 
-	smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+#ifndef CONFIG_ARMV7_PSCI
+	smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
 	smp_kick_all_cpus();
+#endif
 
 	/* call the non-sec switching code on this CPU also */
-	_nonsec_init();
-
+	relocate_secure_section();
+	secure_ram_addr(_nonsec_init)();
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index e0ed3bfb43..1ea086d520 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -34,7 +34,7 @@ void zynq_ddrc_init(void)
 	/* ECC is enabled when memory is in 16bit mode and it is enabled */
 	if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
 	    (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
-		puts("Memory: ECC enabled\n");
+		puts("ECC enabled ");
 		/*
 		 * Clear the first 1MB because it is not initialized from
 		 * first stage bootloader. To get ECC to work all memory has
@@ -42,6 +42,6 @@ void zynq_ddrc_init(void)
 		 */
 		memset((void *)0, 0, 1 * 1024 * 1024);
 	} else {
-		puts("Memory: ECC disabled\n");
+		puts("ECC disabled ");
 	}
 }