keystone2: use EFUSE_BOOTROM information to configure PLLs

This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

3 files changed, 91 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
index 42092e1060..31f66613ef 100644
--- a/arch/arm/cpu/armv7/keystone/clock-k2e.c
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -17,6 +17,22 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
 };
 
+int dev_speeds[] = {
+	SPD800,
+	SPD850,
+	SPD1000,
+	SPD1250,
+	SPD1350,
+	SPD1400,
+	SPD1500,
+	SPD1400,
+	SPD1350,
+	SPD1250,
+	SPD1000,
+	SPD850,
+	SPD800
+};
+
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
index 96a9f72886..1591960795 100644
--- a/arch/arm/cpu/armv7/keystone/clock-k2hk.c
+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
@@ -19,6 +19,38 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
 };
 
+int dev_speeds[] = {
+	SPD800,
+	SPD1000,
+	SPD1200,
+	SPD800,
+	SPD800,
+	SPD800,
+	SPD800,
+	SPD800,
+	SPD1200,
+	SPD1000,
+	SPD800,
+	SPD800,
+	SPD800,
+};
+
+int arm_speeds[] = {
+	SPD800,
+	SPD1000,
+	SPD1200,
+	SPD1350,
+	SPD1400,
+	SPD800,
+	SPD1400,
+	SPD1350,
+	SPD1200,
+	SPD1000,
+	SPD800,
+	SPD800,
+	SPD800,
+};
+
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index 03c1d9f660..30d76a6603 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -11,6 +11,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
+#define MAX_SPEEDS		13
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
 	int i;
@@ -218,3 +220,44 @@ void init_plls(int num_pll, struct pll_init_data *config)
 	for (i = 0; i < num_pll; i++)
 		init_pll(&config[i]);
 }
+
+static int get_max_speed(u32 val, int *speeds)
+{
+	int j;
+
+	if (!val)
+		return speeds[0];
+
+	for (j = 1; j < MAX_SPEEDS; j++) {
+		if (val == 1)
+			return speeds[j];
+		val >>= 1;
+	}
+
+	return SPD800;
+}
+
+#ifdef CONFIG_SOC_K2HK
+static u32 read_efuse_bootrom(void)
+{
+	return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
+		__raw_readl(KS2_REV1_DEVSPEED);
+}
+#else
+static inline u32 read_efuse_bootrom(void)
+{
+	return __raw_readl(KS2_EFUSE_BOOTROM);
+}
+#endif
+
+inline int get_max_dev_speed(void)
+{
+	return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
+}
+
+#ifndef CONFIG_SOC_K2E
+inline int get_max_arm_speed(void)
+{
+	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
+}
+#endif