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authorNishanth Menon <nm@ti.com>2015-03-09 17:12:01 -0500
committerTom Rini <trini@konsulko.com>2015-03-13 09:28:52 -0400
commit5902f4ce0f2bd1411e40dc0ece3598a0fc19b2ae (patch)
tree45f3d8a7d6f3eeedd9686dee52df66f3933f70c2 /arch/arm/cpu/armv7/start.S
parentb45c48a7c30734272371fede01e96f499a314664 (diff)
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ARM: Introduce erratum workaround for 430973
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/start.S')
-rw-r--r--arch/arm/cpu/armv7/start.S13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 8483687879..41fb24cf32 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -202,6 +202,19 @@ skip_errata_798870:
skip_errata_454179:
#endif
+#ifdef CONFIG_ARM_ERRATA_430973
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_430973
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x1 << 6) @ Set IBE bit
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
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