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authorAllen Martin <amartin@nvidia.com>2012-08-31 08:30:00 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:21 +0200
commit00a2749d7be5b0e6cb6435187ec8fea600b44627 (patch)
tree3d3107a9b369a09ba5c40abff80d23788939b48d /arch/arm/cpu/armv7/start.S
parent0d04f34a357d004364b58159b64aad354e65137e (diff)
downloadblackbird-obmc-uboot-00a2749d7be5b0e6cb6435187ec8fea600b44627.tar.gz
blackbird-obmc-uboot-00a2749d7be5b0e6cb6435187ec8fea600b44627.zip
tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/armv7/start.S')
-rw-r--r--arch/arm/cpu/armv7/start.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index aee27fdc4d..38cce938ba 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -133,7 +133,7 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_TEGRA2)
+#if !defined(CONFIG_TEGRA20)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -149,7 +149,7 @@ reset:
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra2 */
+#endif /* !Tegra20 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
@@ -282,14 +282,14 @@ jump_2_ram:
/*
* Move vector table
*/
-#if !defined(CONFIG_TEGRA2)
+#if !defined(CONFIG_TEGRA20)
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
add r0, r0, r9
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra2 */
+#endif /* !Tegra20 */
ldr r0, _board_init_r_ofs
adr r1, _start
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