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| author | Nishanth Menon <nm@ti.com> | 2015-07-27 16:26:06 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-12 20:47:50 -0400 |
| commit | 1bbb556a6a5c0f44d2da32700fce4d279c851e9f (patch) | |
| tree | 14d79050cbb4c40d8f5ef4a285d8decac0cf0c36 /arch/arm/cpu/armv7/omap5 | |
| parent | a615d0be6a73fc48a22e5662608260fe9b9149ff (diff) | |
| download | blackbird-obmc-uboot-1bbb556a6a5c0f44d2da32700fce4d279c851e9f.tar.gz blackbird-obmc-uboot-1bbb556a6a5c0f44d2da32700fce4d279c851e9f.zip | |
ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration
Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 39f8d0d5e2..bc19aebc6d 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -418,3 +418,9 @@ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, { omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); } + +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) +{ + omap_smc1(OMAP5_SERVICE_ACR_SET, acr); +} |
