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| author | Lubomir Popov <lpopov@mm-sol.com> | 2014-12-19 17:34:31 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-29 12:00:49 -0500 |
| commit | b558af81281975d032c063ad228a400d8e619ad5 (patch) | |
| tree | 8cb863af9cd24cb23522341ac17172499b5f96f9 /arch/arm/cpu/armv7/omap5/hw_data.c | |
| parent | 2af13d6b6265a6700c4f65597410b769895024bf (diff) | |
| download | blackbird-obmc-uboot-b558af81281975d032c063ad228a400d8e619ad5.tar.gz blackbird-obmc-uboot-b558af81281975d032c063ad228a400d8e619ad5.zip | |
ARM: OMAP5: DRA7xx: Add support for power rail grouping
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.
This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.
The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 43 |
1 files changed, 24 insertions, 19 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 95f16866e6..b9734fea8f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -320,6 +320,7 @@ struct pmic_data palmas = { .pmic_write = omap_vc_bypass_send_value, }; +/* The TPS659038 and TPS65917 are software-compatible, use common struct */ struct pmic_data tps659038 = { .base_offset = PALMAS_SMPS_BASE_VOLT_UV, .step = 10000, /* 10 mV represented in uV */ @@ -394,34 +395,38 @@ struct vcores_data dra752_volts = { }; struct vcores_data dra722_volts = { - .mpu.value = 1000, + .mpu.value = VDD_MPU_DRA72x, .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, - .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = 0x23, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS65917_REG_ADDR_SMPS1, .mpu.pmic = &tps659038, - .eve.value = 1000, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, - .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = 0x2f, - .eve.pmic = &tps659038, + .core.value = VDD_CORE_DRA72x, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS65917_REG_ADDR_SMPS2, + .core.pmic = &tps659038, - .gpu.value = 1000, + /* + * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x + * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. + */ + .gpu.value = VDD_GPU_DRA72x, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, - .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = 0x2f, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS65917_REG_ADDR_SMPS3, .gpu.pmic = &tps659038, - .core.value = 1000, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, - .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = 0x27, - .core.pmic = &tps659038, + .eve.value = VDD_EVE_DRA72x, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS65917_REG_ADDR_SMPS3, + .eve.pmic = &tps659038, - .iva.value = 1000, + .iva.value = VDD_IVA_DRA72x, .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, - .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = 0x2f, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS65917_REG_ADDR_SMPS3, .iva.pmic = &tps659038, }; |
