ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>

1 files changed, 53 insertions, 34 deletions

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index bddcaed179..44552c342f 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -100,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
-	{250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
-	{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 20 MHz   */
+	{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
 };
 
 static const struct dpll_params
@@ -133,15 +132,14 @@ static const struct dpll_params
 };
 
 static const struct dpll_params
-		core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
-	{266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},		/* 16.8 MHz */
-	{277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},		/* 19.2 MHz */
-	{368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},		/* 26 MHz   */
+		core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+	{266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 12 MHz   */
+	{266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 20 MHz   */
+	{443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 16.8 MHz */
+	{277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 19.2 MHz */
+	{368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},		/* 38.4 MHz */
-	{266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}		/* 20 MHz   */
+	{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 38.4 MHz */
 };
 
 static const struct dpll_params
@@ -187,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
-	{32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
-	{20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
-	{192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */
+	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
+	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
+	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
+	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 38.4 MHz */
-	{96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}		/* 20 MHz   */
+	{10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 38.4 MHz */
 };
 
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@@ -207,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
 	{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
 };
 
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
+	{1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz */
+	{208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
+};
+
 /* ABE M & N values with sys_clk as source */
 static const struct dpll_params
 		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
@@ -224,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = {
 	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 };
 
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */
+static const struct dpll_params
+		abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
+};
+
 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 	{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 20 MHz   */
 	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
 	{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
 	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
 	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
-	{48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 20 MHz   */
 };
 
-static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
-	{533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
+static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
+	{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
-	{533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}		/* 20 MHz   */
+	{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
 };
 
 struct dplls omap5_dplls_es1 = {
@@ -276,10 +293,12 @@ struct dplls omap5_dplls_es2 = {
 
 struct dplls dra7xx_dplls = {
 	.mpu = mpu_dpll_params_1ghz,
-	.core = core_dpll_params_2128mhz_ddr532_dra7xx,
+	.core = core_dpll_params_2128mhz_dra7xx,
 	.per = per_dpll_params_768mhz_dra7xx,
+	.abe = abe_dpll_params_sysclk2_361267khz,
+	.iva = iva_dpll_params_2330mhz_dra7xx,
 	.usb = usb_dpll_params_1920mhz,
-	.ddr = ddr_dpll_params_1066mhz,
+	.ddr = ddr_dpll_params_2128mhz,
 };
 
 struct pmic_data palmas = {