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authorNishanth Menon <nm@ti.com>2015-06-16 08:29:01 -0500
committerTom Rini <trini@konsulko.com>2015-06-19 16:46:48 -0400
commit67055bee25c2add9cece7ceb9967bb67df806529 (patch)
tree1be0f70b0e08d5f5b1b0d5150f1d767242f2cc6b /arch/arm/cpu/armv7/omap5/hw_data.c
parent3683c3d1f784d1e81e31066cecefd320b4ffaed4 (diff)
downloadblackbird-obmc-uboot-67055bee25c2add9cece7ceb9967bb67df806529.tar.gz
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ARM: DRA7: Change configuration to prevent DDR reset control from EMIF
DRA7/AM57xx devices can be operated in many different configurations. When the SoC is supposed to support a configuration where low power mode state may involve the SoC completely powered off and DDR is in self refresh, SoC EMIF controller should not be the master of the reset signal and an external entity might be in control of things. The default configuration of Linux on TI evms involve not powering off the voltage rails (due to various reasons including reliability concerns) and must not allow DDR reset to be controlled by EMIF. On platforms where external entity might control the reset signal, this configuration will be a "dont care". Fixes: 536d87470869 ("ARM: DRA7: Update DDR IO registers") Tested-by: Keerthy <j-keerthy@ti.com> Acked-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index f1a59a3ca9..3a723cace7 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -602,8 +602,8 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
- .ctrl_emif_sdram_config_ext = 0x0001C127,
- .ctrl_emif_sdram_config_ext_final = 0x0001C127,
+ .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
@@ -614,8 +614,8 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
- .ctrl_emif_sdram_config_ext = 0x0001C127,
- .ctrl_emif_sdram_config_ext_final = 0x0001C127,
+ .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
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