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authorXiubo Li <Li.Xiubo@freescale.com>2014-11-21 17:40:54 +0800
committerYork Sun <yorksun@freescale.com>2014-12-11 09:41:30 -0800
commitb8e5c7f94af6b178946ae01ba36ac7fac1e86ec7 (patch)
tree7ad95c3d1ae32f9d515d99fe983e13a898424c13 /arch/arm/cpu/armv7/nonsec_virt.S
parenta7787b78503a2c67fe02f1fcdd995fb6f3830f4b (diff)
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ARM: HYP/non-sec: add the pen address BE mode support.
For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/nonsec_virt.S')
-rw-r--r--arch/arm/cpu/armv7/nonsec_virt.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 745670e549..1ab5d54e30 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -191,6 +191,9 @@ ENTRY(smp_waitloop)
wfi
ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
ldr r1, [r1]
+#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
+ rev r1, r1
+#endif
cmp r0, r1 @ make sure we dont execute this code
beq smp_waitloop @ again (due to a spurious wakeup)
mov r0, r1
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