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authorFabio Estevam <fabio.estevam@freescale.com>2014-06-24 17:40:58 -0300
committerStefano Babic <sbabic@denx.de>2014-07-10 15:29:16 +0200
commit05d54b827fa84b7834fc39c9ff7bb77cce829beb (patch)
tree90f716f445653def78135d210255fbf523ce15e7 /arch/arm/cpu/armv7/mx6
parente153333eeb50021fb3a730a3216c1968e7710999 (diff)
downloadblackbird-obmc-uboot-05d54b827fa84b7834fc39c9ff7bb77cce829beb.tar.gz
blackbird-obmc-uboot-05d54b827fa84b7834fc39c9ff7bb77cce829beb.zip
mx6: Add support for the mx6solox variant
mx6solox is the newest member of the mx6 family. Some of the new features on this variants are: - Cortex M4 microcontroller (besides the CortexA9) - Dual Gigabit Ethernet Add the initial support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c4
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c26
2 files changed, 28 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 7dd83ec9e1..f8da94be1c 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -214,7 +214,7 @@ static u32 get_uart_clk(void)
u32 reg, uart_podf;
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
-#ifdef CONFIG_MX6SL
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
#endif
@@ -282,7 +282,7 @@ static u32 get_emi_slow_clk(void)
return root_freq / (emi_slow_podf + 1);
}
-#ifdef CONFIG_MX6SL
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f20bdebf3f..2012caf2e7 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -79,9 +79,15 @@ u32 __weak get_board_rev(void)
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
+#ifdef CONFIG_MX6SX
+ struct aipstz_regs *aips3;
+#endif
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+#ifdef CONFIG_MX6SX
+ aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+#endif
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -107,6 +113,26 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr2);
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
+
+#ifdef CONFIG_MX6SX
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips3->mprot0);
+ writel(0x77777777, &aips3->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips3->opacr0);
+ writel(0x00000000, &aips3->opacr1);
+ writel(0x00000000, &aips3->opacr2);
+ writel(0x00000000, &aips3->opacr3);
+ writel(0x00000000, &aips3->opacr4);
+#endif
}
static void clear_ldo_ramp(void)
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