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authorPeng Fan <Peng.Fan@freescale.com>2015-01-29 18:03:39 +0800
committerTom Rini <trini@ti.com>2015-01-30 09:19:17 -0500
commit0f274f5376f02ccf30327bf3e5c88d26d3ea8827 (patch)
treec4782c013f59c7a86490048edfdf32d580ca54ce /arch/arm/cpu/armv7/cpu.c
parent2d73f0d6cd42a0ed9a791d665ddbd3d3bf287801 (diff)
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ARM: armv7 fix spelling of SCTRL
SCTLR is the abbreviation of System Control Register, so we should use SCTLR but not SCTRL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/cpu.c')
-rw-r--r--arch/arm/cpu/armv7/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 01cdb7ee76..c56417dd2f 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -53,7 +53,7 @@ int cleanup_before_linux(void)
* After D-cache is flushed and before it is disabled there may
* be some new valid entries brought into the cache. We are sure
* that these lines are not dirty and will not affect our execution.
- * (because unwinding the call-stack and setting a bit in CP15 SCTRL
+ * (because unwinding the call-stack and setting a bit in CP15 SCTLR
* is all we did during this. We have not pushed anything on to the
* stack. Neither have we affected any static data)
* So just invalidate the entire d-cache again to avoid coherency
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