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| author | Sylvain Lemieux <slemieux@tycoint.com> | 2015-07-27 13:37:35 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-17 08:10:58 -0400 |
| commit | 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f (patch) | |
| tree | 858d958c37af0d320bf836cc02cfa67708d2d82c /arch/arm/cpu/arm926ejs | |
| parent | d75b532a9e81a918852a3378e769d07dbfd59f15 (diff) | |
| download | blackbird-obmc-uboot-576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.tar.gz blackbird-obmc-uboot-576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.zip | |
lpc32xx: cpu: add support for soft reset
Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset).
To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c index f757474076..bee9318f5a 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,12 +20,23 @@ void reset_cpu(ulong addr) /* Enable watchdog clock */ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); - /* Reset pulse length is 13005 peripheral clock frames */ - writel(13000, &wdt->pulse); + /* To be compatible with the original U-Boot code: + * addr: - 0: perform hard reset. + * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */ + if (addr == 0) { + /* Reset pulse length is 13005 peripheral clock frames */ + writel(13000, &wdt->pulse); - /* Force WDOG_RESET2 and RESOUT_N signal active */ - writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, - &wdt->mctrl); + /* Force WDOG_RESET2 and RESOUT_N signal active */ + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 + | WDTIM_MCTRL_M_RES2, &wdt->mctrl); + } else { + /* Force match output active */ + writel(0x01, &wdt->emr); + + /* Internal reset on match output (no pulse on "RESOUT_N") */ + writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); + } while (1) /* NOP */; |
