summaryrefslogtreecommitdiffstats
path: root/arch/arm/cpu/arm926ejs/cache.c
diff options
context:
space:
mode:
authorMarek Vasut <marex@denx.de>2012-04-06 03:25:07 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-04-16 22:12:01 +0200
commit2694bb9bcc8ca9636faf38c866dda7bf0529e35f (patch)
treed72a6056cc36814fe67bc19eeaf09206ee192f2d /arch/arm/cpu/arm926ejs/cache.c
parentc6201553ba73616eed0f416f66d28c39691692bd (diff)
downloadblackbird-obmc-uboot-2694bb9bcc8ca9636faf38c866dda7bf0529e35f.tar.gz
blackbird-obmc-uboot-2694bb9bcc8ca9636faf38c866dda7bf0529e35f.zip
ARM926EJS: Fix cache.c to comply with checkpatch.pl
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/cache.c')
-rw-r--r--arch/arm/cpu/arm926ejs/cache.c17
1 files changed, 8 insertions, 9 deletions
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 07f036f18b..2740ad7e29 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -30,7 +30,7 @@
void invalidate_dcache_all(void)
{
- asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
+ asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
}
void flush_dcache_all(void)
@@ -40,7 +40,7 @@ void flush_dcache_all(void)
"mrc p15, 0, r15, c7, c14, 3\n"
"bne 0b\n"
"mcr p15, 0, %0, c7, c10, 4\n"
- ::"r"(0):"memory"
+ : : "r"(0) : "memory"
);
}
@@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
+ asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
@@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
+ asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
- asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
void flush_cache(unsigned long start, unsigned long size)
@@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size)
/*
* Stub implementations for l2 cache operations
*/
-void __l2_cache_disable(void)
-{
-}
+void __l2_cache_disable(void) {}
+
void l2_cache_disable(void)
- __attribute__((weak, alias("__l2_cache_disable")));
+ __attribute__((weak, alias("__l2_cache_disable")));
OpenPOWER on IntegriCloud