Add generic support for samsung s3c2440

This patch adds generic support for the Samsung s3c2440 processor.

Global s3c24x0 changes to struct members converting from upper case to
lower case.

Signed-off-by: Craig Nauman <cnauman@diagraph.com>
Cc: kevin.morfitt@fearnside-systems.co.uk
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

4 files changed, 48 insertions, 27 deletions

diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c
index b13283a798..3ae558dd62 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c
@@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg)
 	ulong r, m, p, s;
 
 	if (pllreg == MPLL)
-		r = readl(&clk_power->MPLLCON);
+		r = readl(&clk_power->mpllcon);
 	else if (pllreg == UPLL)
-		r = readl(&clk_power->UPLLCON);
+		r = readl(&clk_power->upllcon);
 	else
 		hang();
 
@@ -64,7 +64,12 @@ static ulong get_PLLCLK(int pllreg)
 	p = ((r & 0x003F0) >> 4) + 2;
 	s = r & 0x3;
 
+#if defined(CONFIG_S3C2440)
+	if (pllreg == MPLL)
+		return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
+#endif
 	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+
 }
 
 /* return FCLK frequency */
@@ -77,8 +82,23 @@ ulong get_FCLK(void)
 ulong get_HCLK(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-	return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+#ifdef CONFIG_S3C2440
+	switch (readl(&clk_power->clkdivn) & 0x6) {
+	default:
+	case 0:
+		return get_FCLK();
+	case 2:
+		return get_FCLK() / 2;
+	case 4:
+		return (readl(&clk_power->camdivn) & (1 << 9)) ?
+			get_FCLK() / 8 : get_FCLK() / 4;
+	case 6:
+		return (readl(&clk_power->camdivn) & (1 << 8)) ?
+			get_FCLK() / 6 : get_FCLK() / 3;
+	}
+#else
+	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
 }
 
 /* return PCLK frequency */
@@ -86,7 +106,7 @@ ulong get_PCLK(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 
-	return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
 }
 
 /* return UCLK frequency */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c
index 7d47354381..8cf9ff6be0 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void)
 {
 	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
 
-	return readl(&timers->TCNTO4) & 0xffff;
+	return readl(&timers->tcnto4) & 0xffff;
 }
 
 static ulong timestamp;
@@ -56,7 +56,7 @@ int timer_init(void)
 
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
-	writel(0x0f00, &timers->TCFG0);
+	writel(0x0f00, &timers->tcfg0);
 	if (timer_load_val == 0) {
 		/*
 		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
@@ -68,13 +68,13 @@ int timer_init(void)
 	}
 	/* load value for 10 ms timeout */
 	lastdec = timer_load_val;
-	writel(timer_load_val, &timers->TCNTB4);
-	/* auto load, manual update of Timer 4 */
-	tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
-	writel(tmr, &timers->TCON);
-	/* auto load, start Timer 4 */
+	writel(timer_load_val, &timers->tcntb4);
+	/* auto load, manual update of timer 4 */
+	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+	writel(tmr, &timers->tcon);
+	/* auto load, start timer 4 */
 	tmr = (tmr & ~0x0700000) | 0x0500000;
-	writel(tmr, &timers->TCON);
+	writel(tmr, &timers->tcon);
 	timestamp = 0;
 
 	return (0);
@@ -181,6 +181,7 @@ ulong get_tbclk(void)
 	tbclk = timer_load_val * 100;
 #elif defined(CONFIG_SBC2410X) || \
       defined(CONFIG_SMDK2410) || \
+	defined(CONFIG_S3C2440) || \
       defined(CONFIG_VCMA9)
 	tbclk = CONFIG_SYS_HZ;
 #else
@@ -206,13 +207,13 @@ void reset_cpu(ulong ignored)
 	watchdog = s3c24x0_get_base_watchdog();
 
 	/* Disable watchdog */
-	writel(0x0000, &watchdog->WTCON);
+	writel(0x0000, &watchdog->wtcon);
 
 	/* Initialize watchdog timer count register */
-	writel(0x0001, &watchdog->WTCNT);
+	writel(0x0001, &watchdog->wtcnt);
 
 	/* Enable watchdog timer; assert reset at timer timeout */
-	writel(0x0021, &watchdog->WTCON);
+	writel(0x0021, &watchdog->wtcon);
 
 	while (1)
 		/* loop forever and wait for reset to happen */;
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c
index e468ed08fc..226a3f6c90 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/usb.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb.c
@@ -39,14 +39,14 @@ int usb_cpu_init(void)
 	 * Set the 48 MHz UPLL clocking. Values are taken from
 	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
 	 */
-	writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+	writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
 	/* 1 = use pads related USB for USB host */
-	writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
+	writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
 
 	/*
 	 * Enable USB host clock.
 	 */
-	writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
 	return 0;
 }
@@ -55,14 +55,14 @@ int usb_cpu_stop(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 	/* may not want to do this */
-	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
 	return 0;
 }
 
 int usb_cpu_init_fail(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
 	return 0;
 }
 
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
index 5aa8d64a55..ccc97384f3 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void)
 	 * Set the 48 MHz UPLL clocking. Values are taken from
 	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
 	 */
-	clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
-	gpio->MISCCR |= 0x8;	/* 1 = use pads related USB for USB host */
+	clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
+	gpio->misccr |= 0x8;	/* 1 = use pads related USB for USB host */
 
 	/*
 	 * Enable USB host clock.
 	 */
-	clk_power->CLKCON |= (1 << 4);
+	clk_power->clkcon |= (1 << 4);
 
 	memset(&gohci, 0, sizeof(struct ohci));
 	memset(&urb_priv, 0, sizeof(struct urb_priv));
@@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void)
 	if (hc_reset(&gohci) < 0) {
 		hc_release_ohci(&gohci);
 		/* Initialization failed */
-		clk_power->CLKCON &= ~(1 << 4);
+		clk_power->clkcon &= ~(1 << 4);
 		return -1;
 	}
 
@@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void)
 		err("can't start usb-%s", gohci.slot_name);
 		hc_release_ohci(&gohci);
 		/* Initialization failed */
-		clk_power->CLKCON &= ~(1 << 4);
+		clk_power->clkcon &= ~(1 << 4);
 		return -1;
 	}
 #ifdef	DEBUG
@@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void)
 	/* call hc_release_ohci() here ? */
 	hc_reset(&gohci);
 	/* may not want to do this */
-	clk_power->CLKCON &= ~(1 << 4);
+	clk_power->clkcon &= ~(1 << 4);
 	return 0;
 }