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authorPhilip Paeps <philip@paeps.cx>2013-04-09 12:44:31 +0000
committerStefano Babic <sbabic@denx.de>2013-04-16 18:58:47 +0200
commit04f79536c3fee3bef1ceb259c303b69100e0baf7 (patch)
tree70b11056d525a0c91f1bf918fcfab8808bc25880 /arch/arm/cpu/arm1136
parentc4a4e2e20ca226948b62ed116df98f7a3932f2ac (diff)
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mx35 iomux: correct offsets of IOMUX registers
This makes mxc_iomux_set_input() work correctly. Previously, the incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input() to write to the wrong register, possibly resulting in unexpected behaviour. Signed-off-by: Philip Paeps <philip@paeps.cx> Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/arm1136')
-rw-r--r--arch/arm/cpu/arm1136/mx35/iomux.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c
index a302575eda..698909e4a4 100644
--- a/arch/arm/cpu/arm1136/mx35/iomux.c
+++ b/arch/arm/cpu/arm1136/mx35/iomux.c
@@ -34,8 +34,8 @@ enum iomux_reg_addr {
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */
- IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */
+ IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x7A4, /* last Pad control */
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7A8, /* input select */
IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */
};
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