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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2013-07-02 09:21:04 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:40 -0700 |
| commit | 64501c669851e45dd47699349dae6b5798c075a3 (patch) | |
| tree | 9ac713a2c30d740ea29a0888d9ca357b89db1ed3 /README | |
| parent | 17b8614754e9adc531d3f1bc3db66bf680a09447 (diff) | |
| download | blackbird-obmc-uboot-64501c669851e45dd47699349dae6b5798c075a3.tar.gz blackbird-obmc-uboot-64501c669851e45dd47699349dae6b5798c075a3.zip | |
board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -406,10 +406,18 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. + CONFIG_SYS_FSL_DSP_DDR_ADDR + This value denotes start offset of DDR memory which is + connected exclusively to the DSP cores. + CONFIG_SYS_FSL_DSP_M2_RAM_ADDR This value denotes start offset of M2 memory which is directly connected to the DSP core. + CONFIG_SYS_FSL_DSP_M3_RAM_ADDR + This value denotes start offset of M3 memory which is directly + connected to the DSP core. + CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. |
