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authorRuchika Gupta <ruchika.gupta@freescale.com>2014-09-09 11:50:31 +0530
committerYork Sun <yorksun@freescale.com>2014-10-16 14:16:50 -0700
commit028dbb8db1d18c5835ab34659f9ef7a516571524 (patch)
treeb6c94157e8a8483a025b2ec4591df115422fe3ae /README
parent48ef0d2a1002d3da0bf7ed13d0959bcbf782c792 (diff)
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fsl_sec : Change accessor function to take care of endianness
SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
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1 files changed, 6 insertions, 0 deletions
diff --git a/README b/README
index 46def0086b..19abe20035 100644
--- a/README
+++ b/README
@@ -544,6 +544,12 @@ The following options need to be configured:
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
+ CONFIG_SYS_FSL_SEC_BE
+ Defines the SEC controller register space as Big Endian
+
+ CONFIG_SYS_FSL_SEC_LE
+ Defines the SEC controller register space as Little Endian
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
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