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authorStefan Roese <sr@denx.de>2007-01-06 15:58:09 +0100
committerStefan Roese <sr@denx.de>2007-01-06 15:58:09 +0100
commitf07ae7a9daef27a3d0213a4f3fe39d5342173c02 (patch)
tree8eab8ab98b9e095f59094f91e9132a180c07aa4e
parentf16c1da9577f06c5fc08651a4065537407de4635 (diff)
downloadblackbird-obmc-uboot-f07ae7a9daef27a3d0213a4f3fe39d5342173c02.tar.gz
blackbird-obmc-uboot-f07ae7a9daef27a3d0213a4f3fe39d5342173c02.zip
[PATCH] 44x: Fix problem with DDR controller setup (refresh rate)
This patch fixes a problem with an incorrect setup for the refresh timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--cpu/ppc4xx/sdram.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index f06038e998..294b89cb2a 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -380,7 +380,7 @@ long int initdram(int board_type)
mtsdram(mem_b0cr, mb0cf[i].reg);
mtsdram(mem_tr0, 0x41094012);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20s @ 133MHz PLB*/
+ mtsdram(mem_rtr, 0x04100000); /* Interval 7.8s @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */
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