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| author | Wolfgang Denk <wd@denx.de> | 2011-10-12 22:43:54 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-12 22:43:54 +0200 |
| commit | e5a07171767115b446fb5070e9c0293fd1190c03 (patch) | |
| tree | 70cfb4b26418d51b870d567f6578621843348ef1 | |
| parent | 37eefe80bb3f1cc25dc8b10f2b7d0b8077e60e09 (diff) | |
| parent | 60161943719c4054453f6932ad2bd5fe2285bf1b (diff) | |
| download | blackbird-obmc-uboot-e5a07171767115b446fb5070e9c0293fd1190c03.tar.gz blackbird-obmc-uboot-e5a07171767115b446fb5070e9c0293fd1190c03.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
* 'master' of git://git.denx.de/u-boot-nand-flash:
NAND: davinci: choose correct 1-bit h/w ECC reg
| -rw-r--r-- | drivers/mtd/nand/davinci_nand.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d41579c9ce..e8506ddd9b 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -176,35 +176,35 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, #ifdef CONFIG_SYS_NAND_HW_ECC -static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) { - u_int32_t val; + u_int32_t ecc = 0; - (void)__raw_readl(&(davinci_emif_regs->nandfecc[ + ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ CONFIG_SYS_NAND_CS - 2])); - val = __raw_readl(&davinci_emif_regs->nandfcr); - val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); - val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); - __raw_writel(val, &davinci_emif_regs->nandfcr); + return ecc; } -static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) +static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - u_int32_t ecc = 0; + u_int32_t val; - ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1])); + /* reading the ECC result register resets the ECC calculation */ + nand_davinci_readecc(mtd); - return ecc; + val = __raw_readl(&davinci_emif_regs->nandfcr); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + __raw_writel(val, &davinci_emif_regs->nandfcr); } static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { u_int32_t tmp; - const int region = 1; - tmp = nand_davinci_readecc(mtd, region); + tmp = nand_davinci_readecc(mtd); /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */ |
