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authorLokesh Vutla <lokeshvutla@ti.com>2015-08-28 12:28:25 +0530
committerTom Rini <trini@konsulko.com>2015-09-11 14:05:36 -0400
commitd6927a5d10c3702728d1c77f008229863874de95 (patch)
treee5022bc0d0ff83256fa481067fad2ee5fd30d0ec
parentbab8d1e2280f039fbbb3039ec4750e54091b6113 (diff)
downloadblackbird-obmc-uboot-d6927a5d10c3702728d1c77f008229863874de95.tar.gz
blackbird-obmc-uboot-d6927a5d10c3702728d1c77f008229863874de95.zip
ARM: DRA7: emif: Fix disabling/enabling of refreshes
clrsetbits_le32/clrbits_le32 takes mask of the bits as input that are needed to be set/clear. But emif driver passes the shift of the bits. Fixing it here. Reported-by: Mark Mckeown <m-mckeown@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index f5b22f6a78..bf7bf262c7 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -294,8 +294,8 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
/* Disable refreshed before leveling */
- clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
- EMIF_REG_INITREF_DIS_SHIFT);
+ clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
+ EMIF_REG_INITREF_DIS_MASK);
/* Start Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
@@ -309,7 +309,7 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
}
/* Enable refreshes after leveling */
- clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
debug("HW leveling success\n");
/*
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