arm: Remove pxa255_idp, zipitz2 boards

These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>

17 files changed, 0 insertions, 1457 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a3a6c6e6b1..e96e902ffd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -639,10 +639,6 @@ config TARGET_PALMTREO680
 	select CPU_PXA
 	select SUPPORT_SPL
 
-config TARGET_PXA255_IDP
-	bool "Support pxa255_idp"
-	select CPU_PXA
-
 config TARGET_VPAC270
 	bool "Support vpac270"
 	select CPU_PXA
@@ -652,10 +648,6 @@ config TARGET_XAENIAX
 	bool "Support xaeniax"
 	select CPU_PXA
 
-config TARGET_ZIPITZ2
-	bool "Support zipitz2"
-	select CPU_PXA
-
 config TARGET_COLIBRI_PXA270
 	bool "Support colibri_pxa270"
 	select CPU_PXA
@@ -792,7 +784,6 @@ source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/palmtreo680/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/ppcag/bg0900/Kconfig"
-source "board/pxa255_idp/Kconfig"
 source "board/samsung/smdk2410/Kconfig"
 source "board/sandisk/sansa_fuze_plus/Kconfig"
 source "board/scb9328/Kconfig"
@@ -825,7 +816,6 @@ source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
 source "board/xaeniax/Kconfig"
-source "board/zipitz2/Kconfig"
 
 source "arch/arm/Kconfig.debug"
 
diff --git a/board/pxa255_idp/Kconfig b/board/pxa255_idp/Kconfig
deleted file mode 100644
index 544831199d..0000000000
--- a/board/pxa255_idp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PXA255_IDP
-
-config SYS_BOARD
-	default "pxa255_idp"
-
-config SYS_CONFIG_NAME
-	default "pxa255_idp"
-
-endif
diff --git a/board/pxa255_idp/MAINTAINERS b/board/pxa255_idp/MAINTAINERS
deleted file mode 100644
index 24d723602c..0000000000
--- a/board/pxa255_idp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PXA255_IDP BOARD
-M:	Cliff Brake <cliff.brake@gmail.com>
-S:	Maintained
-F:	board/pxa255_idp/
-F:	include/configs/pxa255_idp.h
-F:	configs/pxa255_idp_defconfig
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
deleted file mode 100644
index 59d696741d..0000000000
--- a/board/pxa255_idp/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pxa_idp.o
diff --git a/board/pxa255_idp/README b/board/pxa255_idp/README
deleted file mode 100644
index 0cc2f2ae33..0000000000
--- a/board/pxa255_idp/README
+++ /dev/null
@@ -1,11 +0,0 @@
-Tested:
-
-- MMC
-- Ethernet
-- BL console (on serial port connector J5)
-- flash support
-
-Todo:
-
-- display support
-- PCMCIA support
diff --git a/board/pxa255_idp/idp_notes.txt b/board/pxa255_idp/idp_notes.txt
deleted file mode 100644
index 47467485fe..0000000000
--- a/board/pxa255_idp/idp_notes.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Notes on the Vibren PXA255 IDP.
-
-Chip select usage:
-
-CS0 - flash
-CS1 - alt flash (Mdoc or main flash)
-CS2 - high speed expansion bus
-CS3 - Media Q, low speed exp bus
-CS4 - low speed exp bus
-CS5 - low speed exp bus
-  - IDE: offset 0x03000000 (abs: 0x17000000)
-  - Eth: offset 0x03400000 (abs: 0x17400000)
-  - core voltage latch: offset 0x03800000 (abs: 0x17800000)
-  - CPLD: offset 0x03C00000 (abs: 0x17C00000)
-
-PCMCIA Power control
-
-MAX1602EE w/ code pulled high (Cirrus code)
-vx = 5v
-vy = 3v
-
-			Bit pattern
-			PWR 3,2,1,0
-vcc	     vpp	A1VCC  A0VCC   A1VPP   A0VPP
-=====================================================
-0	     0            0      0       0       0	0x0
-3 (vy)	     0            1      0       1       1	0xB
-3 (vy)	     3 (vy)       1      0       0       1	0x9
-3 (vy)	     12(12in)     1      0       1       0	0xA
-5 (vx)	     0            0      1       1       1	0x7
-5 (vx)	     5 (vx)       0      1       0       1	0x5
-5 (vx	     12(12in)     0      1       1       0	0x6
-
-Display power sequencing:
-
-- VDD applied
-- within 1sec, activate scanning signals
-- wait at least 50mS - scanning signals must be active before activating DISP
-
-Signal mapping:
-Schematic            LV8V31 signal name
-=========================================
-LCD_ENAVLCD		DISP
-LCD_PWR			Applies VDD to board
-
-Both of the above signals are controlled by the CPLD
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
deleted file mode 100644
index 197ff3ef31..0000000000
--- a/board/pxa255_idp/pxa_idp.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2004
- * BEC Systems <http://bec-systems.com>
- * Cliff Brake <cliff.brake@gmail.com>
- * Support for Accelent/Vibren PXA255 IDP
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* We have RAM, disable cache */
-	dcache_disable();
-	icache_disable();
-
-	/* arch number of Lubbock-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	/* turn on serial ports */
-	*(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
-
-	/* set PWM for LCD */
-	/* a value that works is 60Hz, 77% duty cycle */
-	writel(readl(CKEN) | CKEN0_PWM0, CKEN);
-	writel(0x3f, PWM_CTRL0);
-	writel(0x3ff, PWM_PERVAL0);
-	writel(792, PWM_PWDUTY0);
-
-	/* clear reset to AC97 codec */
-	writel(readl(CKEN) | CKEN2_AC97, CKEN);
-	writel(GCR_COLD_RST, GCR);
-
-	/* enable LCD backlight */
-	/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
-
-	/* test display */
-	/* lcd_puts("This is a test\nTest #2\n"); */
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
-	pxa_mmc_register(0);
-	return 0;
-}
-#endif
-
-int board_late_init(void)
-{
-	setenv("stdout", "serial");
-	setenv("stderr", "serial");
-	return 0;
-}
-
-int dram_init(void)
-{
-	pxa2xx_dram_init();
-	gd->ram_size = PHYS_SDRAM_1_SIZE;
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef DEBUG_BLINKC_ENABLE
-
-void delay_c(void)
-{
-	/* reset OSCR to 0 */
-	writel(0, OSCR);
-	while (readl(OSCR) > 0x10000)
-		;
-
-	while (readl(OSCR) < 0xd4000)
-		;
-}
-
-void blink_c(void)
-{
-	int led_bit = (1<<10);
-
-	writel(led_bit, GPDR0);
-	writel(led_bit, GPCR0);
-	delay_c();
-	writel(led_bit, GPSR0);
-	delay_c();
-	writel(led_bit, GPCR0);
-}
-
-int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	printf("IDPCMD started\n");
-	return 0;
-}
-
-U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
-	   "custom IDP command",
-	   "no args at this time"
-);
-
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out
deleted file mode 100644
index 39295fb679..0000000000
--- a/board/pxa255_idp/pxa_reg_calcs.out
+++ /dev/null
@@ -1,119 +0,0 @@
-gafr0_l: 0x80001005
-gafr0_u: 0xa5128012
-gafr1_l: 0x699a9558
-gafr1_u: 0xaaa5aa6a
-gafr2_l: 0xaaaaaaaa
-gafr2_u: 0x2
-gpcr0: 0x1800400
-gpcr1: 0x0
-gpcr2: 0x0
-gpdr0: 0xc1818440
-gpdr1: 0xfcffab82
-gpdr2: 0x1ffff
-gpsr0: 0x8000
-gpsr1: 0x3f0002
-gpsr2: 0x1c000
-
-
-#define CONFIG_SYS_GAFR0_L_VAL	0x80001005
-#define CONFIG_SYS_GAFR0_U_VAL	0xa5128012
-#define CONFIG_SYS_GAFR1_L_VAL	0x699a9558
-#define CONFIG_SYS_GAFR1_U_VAL	0xaaa5aa6a
-#define CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL	0x2
-#define CONFIG_SYS_GPCR0_VAL	0x1800400
-#define CONFIG_SYS_GPCR1_VAL	0x0
-#define CONFIG_SYS_GPCR2_VAL	0x0
-#define CONFIG_SYS_GPDR0_VAL	0xc1818440
-#define CONFIG_SYS_GPDR1_VAL	0xfcffab82
-#define CONFIG_SYS_GPDR2_VAL	0x1ffff
-#define CONFIG_SYS_GPSR0_VAL	0x8000
-#define CONFIG_SYS_GPSR1_VAL	0x3f0002
-#define CONFIG_SYS_GPSR2_VAL	0x1c000
-
-
-GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
-GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
-GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
-GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
-GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
-GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
-GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
-GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
-GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
-GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
-GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
-GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
-GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
-GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
-GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
-GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
-GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
-GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
-GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
-GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
-GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
-GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
-GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
-GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
-GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
-GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
-GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
-GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
-GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
-GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
-GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
-GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
-GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
-GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
-GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
-GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
-GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
-GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
-GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
-GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
-GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
-GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
-GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
-GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
-GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
-GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
-GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
-GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
-GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
-GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
-GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
-GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
-GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
-GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
-GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
-GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
-GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
-GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
-GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
-GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
-GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
-GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
-GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
-GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
-GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
-GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
-GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
-GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
-GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
-GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
-GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
-GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
-GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
-GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
-GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
-GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
-GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
-GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
-GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
-GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
-GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
-GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py
deleted file mode 100644
index 4a721d1b04..0000000000
--- a/board/pxa255_idp/pxa_reg_calcs.py
+++ /dev/null
@@ -1,298 +0,0 @@
-#!/usr/bin/python
-
-# (C) Copyright 2004
-# BEC Systems <http://bec-systems.com>
-# Cliff Brake <cliff.brake@gmail.com>
-
-# SPDX-License-Identifier:	GPL-2.0+
-
-# calculations for PXA255 registers
-
-class gpio:
-	dir = '0'
-	set = '0'
-	clr = '0'
-	alt = '0'
-	desc = ''
-
-	def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
-		self.dir = dir
-		self.set = set
-		self.clr = clr
-		self.alt = alt
-		self.desc = desc
-		
-
-# the following is a dictionary of all GPIOs in the system
-# the key is the GPIO number
-
-
-pxa255_alt_func = {
-	0: ['gpio', 'none', 'none', 'none'],
-	1: ['gpio', 'gpio reset', 'none', 'none'],
-	2: ['gpio', 'none', 'none', 'none'],
-	3: ['gpio', 'none', 'none', 'none'],
-	4: ['gpio', 'none', 'none', 'none'],
-	5: ['gpio', 'none', 'none', 'none'],
-	6: ['gpio', 'MMC clk', 'none', 'none'],
-	7: ['gpio', '48MHz clock', 'none', 'none'],
-	8: ['gpio', 'MMC CS0', 'none', 'none'],
-	9: ['gpio', 'MMC CS1', 'none', 'none'],
-	10: ['gpio', 'RTC Clock', 'none', 'none'],
-	11: ['gpio', '3.6MHz', 'none', 'none'],
-	12: ['gpio', '32KHz', 'none', 'none'],
-	13: ['gpio', 'none', 'MBGNT', 'none'],
-	14: ['gpio', 'MBREQ', 'none', 'none'],
-	15: ['gpio', 'none', 'nCS_1', 'none'],
-	16: ['gpio', 'none', 'PWM0', 'none'],
-	17: ['gpio', 'none', 'PWM1', 'none'],
-	18: ['gpio', 'RDY', 'none', 'none'],
-	19: ['gpio', 'DREQ[1]', 'none', 'none'],
-	20: ['gpio', 'DREQ[0]', 'none', 'none'],
-	21: ['gpio', 'none', 'none', 'none'],
-	22: ['gpio', 'none', 'none', 'none'],
-	23: ['gpio', 'none', 'SSP SCLK', 'none'],
-	24: ['gpio', 'none', 'SSP SFRM', 'none'],
-	25: ['gpio', 'none', 'SSP TXD', 'none'],
-	26: ['gpio', 'SSP RXD', 'none', 'none'],
-	27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
-	28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
-	29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
-	30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
-	31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
-	32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
-	33: ['gpio', 'none', 'nCS_5', 'none'],
-	34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
-	35: ['gpio', 'FF CTS', 'none', 'none'],
-	36: ['gpio', 'FF DCD', 'none', 'none'],
-	37: ['gpio', 'FF DSR', 'none', 'none'],
-	38: ['gpio', 'FF RI', 'none', 'none'],
-	39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
-	40: ['gpio', 'none', 'FF DTR', 'none'],
-	41: ['gpio', 'none', 'FF RTS', 'none'],
-	42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
-	43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
-	44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
-	45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
-	46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
-	47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
-	48: ['gpio', 'HW TXD', 'nPOE', 'none'],
-	49: ['gpio', 'HW RXD', 'nPWE', 'none'],
-	50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
-	51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
-	52: ['gpio', 'none', 'nPCE[1]', 'none'],
-	53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
-	54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
-	55: ['gpio', 'none', 'nPREG', 'none'],
-	56: ['gpio', 'nPWAIT', 'none', 'none'],
-	57: ['gpio', 'nIOIS16', 'none', 'none'],
-	58: ['gpio', 'none', 'LDD[0]', 'none'],
-	59: ['gpio', 'none', 'LDD[1]', 'none'],
-	60: ['gpio', 'none', 'LDD[2]', 'none'],
-	61: ['gpio', 'none', 'LDD[3]', 'none'],
-	62: ['gpio', 'none', 'LDD[4]', 'none'],
-	63: ['gpio', 'none', 'LDD[5]', 'none'],
-	64: ['gpio', 'none', 'LDD[6]', 'none'],
-	65: ['gpio', 'none', 'LDD[7]', 'none'],
-	66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
-	67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
-	68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
-	69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
-	70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
-	71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
-	72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
-	73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
-	74: ['gpio', 'none', 'LCD_FCLK', 'none'],
-	75: ['gpio', 'none', 'LCD_LCLK', 'none'],
-	76: ['gpio', 'none', 'LCD_PCLK', 'none'],
-	77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
-	78: ['gpio', 'none', 'nCS_2', 'none'],
-	79: ['gpio', 'none', 'nCS_3', 'none'],
-	80: ['gpio', 'none', 'nCS_4', 'none'],
-	81: ['gpio', 'NSSPSCLK', 'none', 'none'],
-	82: ['gpio', 'NSSPSFRM', 'none', 'none'],
-	83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
-	84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
-}
-
-
-#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
-
-gpio_list = []
-
-for i in range(0,85):
-	gpio_list.append(gpio())
-
-#chip select GPIOs
-gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
-gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
-gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
-gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
-gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
-gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
-gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
-gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
-gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
-gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
-gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
-gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
-gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
-
-# PCMCIA stuff
-gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
-gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
-gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
-gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
-gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
-gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
-gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
-gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
-gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
-gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
-
-# SSP port
-gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
-gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
-gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
-gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
-gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
-
-# audio codec
-gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
-gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
-gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
-gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
-gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
-
-# serial ports
-gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
-gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
-gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
-gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
-gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
-gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
-gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
-gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
-
-gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
-gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
-gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
-gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
-
-gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
-gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
-
-# misc GPIO signals
-gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
-gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
-gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
-gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
-gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
-gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
-gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
-gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
-gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
-gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
-gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
-gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
-gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
-gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
-gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
-
-# LCD GPIOs
-gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
-gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
-gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
-gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
-gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
-gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
-gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
-gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
-gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
-gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
-gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
-gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
-gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
-gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
-gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
-gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
-gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
-gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
-gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
-gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
-
-# calculate registers
-pxa_regs = {
-	'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
-	'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
-	'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
-	'gafr0_l':0, 'gafr0_u':0,
-	'gafr1_l':0, 'gafr1_u':0,
-	'gafr2_l':0, 'gafr2_u':0,
-}
-
-# U-boot define names
-uboot_reg_names = {
-	'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL',
-	'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL',
-	'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL',
-	'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL',
-	'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL',
-	'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL',
-}
-
-# bit mappings
-
-bit_mappings = [
-
-{ 'gpio':(0,32),  'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
-{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
-{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
-{ 'gpio':(0,16),  'shift':2, 'regs':{'alt':'gafr0_l'} },
-{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
-{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
-{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
-{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
-{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
-
-]
-
-def stuff_bits(bit_mapping, gpio_list):
-	gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
-
-	for gpio in gpios:
-		for reg in bit_mapping['regs'].keys():
-			value = eval( 'gpio_list[gpio].%s' % (reg) )
-			if ( value ):
-				# we have a high bit
-				bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
-				bit = value << (bit_shift)
-				pxa_regs[bit_mapping['regs'][reg]] |= bit
-
-for i in bit_mappings:
-	stuff_bits(i, gpio_list)
-
-# now print out all regs
-registers = pxa_regs.keys()
-registers.sort()
-for reg in registers:
-	print '%s: 0x%x' % (reg, pxa_regs[reg])
-
-# print define to past right into U-Boot source code
-
-print 
-print 
-
-for reg in registers:
-	print '#define %s	0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
-
-# print all GPIOS
-print
-print
-
-for i in range(len(gpio_list)):
-	gpio_i = gpio_list[i]
-	alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
-	print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
-
-
diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig
deleted file mode 100644
index c6635040a3..0000000000
--- a/board/zipitz2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ZIPITZ2
-
-config SYS_BOARD
-	default "zipitz2"
-
-config SYS_CONFIG_NAME
-	default "zipitz2"
-
-endif
diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS
deleted file mode 100644
index 55b0f6406c..0000000000
--- a/board/zipitz2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ZIPITZ2 BOARD
-M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Maintained
-F:	board/zipitz2/
-F:	include/configs/zipitz2.h
-F:	configs/zipitz2_defconfig
diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile
deleted file mode 100644
index 855f6bcda8..0000000000
--- a/board/zipitz2/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (C) 2009
-# Marek Vasut <marek.vasut@gmail.com>
-#
-# Heavily based on pxa255_idp platform
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= zipitz2.o
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
deleted file mode 100644
index 90bba6a5fc..0000000000
--- a/board/zipitz2/zipitz2.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (C) 2009
- * Marek Vasut <marek.vasut@gmail.com>
- *
- * Heavily based on pxa255_idp platform
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-#include <spi.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef	CONFIG_CMD_SPI
-void lcd_start(void);
-#else
-inline void lcd_start(void) {};
-#endif
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* We have RAM, disable cache */
-	dcache_disable();
-	icache_disable();
-
-	/* arch number of Z2 */
-	gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	/* Enable LCD */
-	lcd_start();
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	pxa2xx_dram_init();
-	gd->ram_size = PHYS_SDRAM_1_SIZE;
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef	CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
-	pxa_mmc_register(0);
-	return 0;
-}
-#endif
-
-#ifdef	CONFIG_CMD_SPI
-
-struct {
-	unsigned char	reg;
-	unsigned short	data;
-	unsigned char	mdelay;
-} lcd_data[] = {
-	{ 0x07,	0x0000,	0 },
-	{ 0x13,	0x0000,	10 },
-	{ 0x11,	0x3004,	0 },
-	{ 0x14,	0x200F,	0 },
-	{ 0x10,	0x1a20,	0 },
-	{ 0x13,	0x0040,	50 },
-	{ 0x13,	0x0060,	0 },
-	{ 0x13,	0x0070,	200 },
-	{ 0x01,	0x0127,	0 },
-	{ 0x02,	0x0700,	0 },
-	{ 0x03,	0x1030,	0 },
-	{ 0x08,	0x0208,	0 },
-	{ 0x0B,	0x0620,	0 },
-	{ 0x0C,	0x0110,	0 },
-	{ 0x30,	0x0120,	0 },
-	{ 0x31,	0x0127,	0 },
-	{ 0x32,	0x0000,	0 },
-	{ 0x33,	0x0503,	0 },
-	{ 0x34,	0x0727,	0 },
-	{ 0x35,	0x0124,	0 },
-	{ 0x36,	0x0706,	0 },
-	{ 0x37,	0x0701,	0 },
-	{ 0x38,	0x0F00,	0 },
-	{ 0x39,	0x0F00,	0 },
-	{ 0x40,	0x0000,	0 },
-	{ 0x41,	0x0000,	0 },
-	{ 0x42,	0x013f,	0 },
-	{ 0x43,	0x0000,	0 },
-	{ 0x44,	0x013f,	0 },
-	{ 0x45,	0x0000,	0 },
-	{ 0x46,	0xef00,	0 },
-	{ 0x47,	0x013f,	0 },
-	{ 0x48,	0x0000,	0 },
-	{ 0x07,	0x0015,	30 },
-	{ 0x07,	0x0017,	0 },
-	{ 0x20,	0x0000,	0 },
-	{ 0x21,	0x0000,	0 },
-	{ 0x22,	0x0000,	0 },
-};
-
-void zipitz2_spi_sda(int set)
-{
-	/* GPIO 13 */
-	if (set)
-		writel((1 << 13), GPSR0);
-	else
-		writel((1 << 13), GPCR0);
-}
-
-void zipitz2_spi_scl(int set)
-{
-	/* GPIO 22 */
-	if (set)
-		writel((1 << 22), GPCR0);
-	else
-		writel((1 << 22), GPSR0);
-}
-
-unsigned char zipitz2_spi_read(void)
-{
-	/* GPIO 40 */
-	return !!(readl(GPLR1) & (1 << 8));
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	/* Always valid */
-	return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	/* GPIO 88 low */
-	writel((1 << 24), GPCR2);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	/* GPIO 88 high */
-	writel((1 << 24), GPSR2);
-
-}
-
-void lcd_start(void)
-{
-	int i;
-	unsigned char reg[3] = { 0x74, 0x00, 0 };
-	unsigned char data[3] = { 0x76, 0, 0 };
-	unsigned char dummy[3] = { 0, 0, 0 };
-
-	/* PWM2 AF */
-	writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
-	/* Enable clock to all PWM */
-	writel(readl(CKEN) | 0x3, CKEN);
-	/* Configure PWM2 */
-	writel(0x4f, PWM_CTRL2);
-	writel(0x2ff, PWM_PWDUTY2);
-	writel(792, PWM_PERVAL2);
-
-	/* Toggle the reset pin to reset the LCD */
-	writel((1 << 19), GPSR0);
-	udelay(100000);
-	writel((1 << 19), GPCR0);
-	udelay(20000);
-	writel((1 << 19), GPSR0);
-	udelay(20000);
-
-	/* Program the LCD init sequence */
-	for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
-		reg[0] = 0x74;
-		reg[1] = 0x0;
-		reg[2] = lcd_data[i].reg;
-		spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
-		data[0] = 0x76;
-		data[1] = lcd_data[i].data >> 8;
-		data[2] = lcd_data[i].data & 0xff;
-		spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
-		if (lcd_data[i].mdelay)
-			udelay(lcd_data[i].mdelay * 1000);
-	}
-
-	writel((1 << 11), GPSR0);
-}
-#endif
diff --git a/configs/pxa255_idp_defconfig b/configs/pxa255_idp_defconfig
deleted file mode 100644
index c7be4e9b33..0000000000
--- a/configs/pxa255_idp_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_PXA255_IDP=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
deleted file mode 100644
index 2977ccc8dd..0000000000
--- a/configs/zipitz2_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_ZIPITZ2=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
deleted file mode 100644
index 332d79f89f..0000000000
--- a/include/configs/pxa255_idp.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copied from lubbock.h
- *
- * (C) Copyright 2004
- * BEC Systems <http://bec-systems.com>
- * Cliff Brake <cliff.brake@gmail.com>
- * Configuation settings for the Accelent/Vibren PXA255 IDP
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/pxa-regs.h>
-
-/*
- * If we are developing, we might want to start U-Boot from RAM
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#undef CONFIG_SKIP_LOWLEVEL_INIT			/* define for developing */
-#define	CONFIG_SYS_TEXT_BASE	0x0
-
-/*
- * define the following to enable debug blinks.  A debug blink function
- * must be defined in memsetup.S
- */
-#undef DEBUG_BLINK_ENABLE
-#undef DEBUG_BLINKC_ENABLE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_PXA25X		1	/* This is an PXA250 CPU    */
-
-#undef CONFIG_LCD
-#ifdef CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-
-#define CONFIG_MMC		1
-#define CONFIG_DOS_PARTITION	1
-#define CONFIG_BOARD_LATE_INIT
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * PXA250 IDP memory map information
- */
-
-#define IDP_CS5_ETH_OFFSET	0x03400000
-
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE	(PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
-#define CONFIG_SMC_USE_32_BIT	1
-/* #define CONFIG_SMC_USE_IOFUNCS */
-
-/* the following has to be set high -- suspect something is wrong with
- * with the tftp timeout routines. FIXME!!!
- */
-#define CONFIG_NET_RETRY_COUNT	100
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
-#define CONFIG_CONS_INDEX	3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTCOMMAND	"bootm 40000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-/* #define CONFIG_INITRD_TAG		1 */
-
-/*
- * Current memory map for Vibren supplied Linux images:
- *
- * Flash:
- * 0 - 0x3ffff (size = 0x40000): bootloader
- * 0x40000 - 0x13ffff (size = 0x100000): kernel
- * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
- *
- * RAM:
- * 0xa0008000 - kernel is loaded
- * 0xa3000000 - Uboot runs (48MB into RAM)
- *
- */
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"prog_boot_mmc="						\
-			"mw.b 0xa0000000 0xff 0x40000; "		\
-			"if	 mmcinit && "				\
-				"fatload mmc 0 0xa0000000 u-boot.bin; "	\
-			"then "						\
-				"protect off 0x0 0x3ffff; "		\
-				"erase 0x0 0x3ffff; "			\
-				"cp.b 0xa0000000 0x0 0x40000; "		\
-				"reset;"				\
-			"fi\0"						\
-	"prog_uzImage_mmc="						\
-			"mw.b 0xa0000000 0xff 0x100000; "		\
-			"if	 mmcinit && "				\
-				"fatload mmc 0 0xa0000000 uzImage; "	\
-			"then "						\
-				"protect off 0x40000 0xfffff; "		\
-				"erase 0x40000 0xfffff; "		\
-				"cp.b 0xa0000000 0x40000 0x100000; "	\
-			"fi\0"						\
-	"prog_jffs_mmc="						\
-			"mw.b 0xa0000000 0xff 0x1e00000; "		\
-			"if	 mmcinit && "				\
-				"fatload mmc 0 0xa0000000 root.jffs; "	\
-			"then "						\
-				"protect off 0x140000 0x1f3ffff; "	\
-				"erase 0x140000 0x1f3ffff; "		\
-				"cp.b 0xa0000000 0x140000 0x1e00000; "	\
-			"fi\0"						\
-	"boot_mmc="							\
-			"if	 mmcinit && "				\
-				"fatload mmc 0 0xa1000000 uzImage && "	\
-			"then "						\
-				"bootm 0xa1000000; "			\
-			"fi\0"						\
-	"prog_boot_net="						\
-			"mw.b 0xa0000000 0xff 0x100000; "		\
-			"if	 bootp 0xa0000000 u-boot.bin; "		\
-			"then "						\
-				"protect off 0x0 0x3ffff; "		\
-				"erase 0x0 0x3ffff; "			\
-				"cp.b 0xa0000000 0x0 0x40000; "		\
-				"reset; "				\
-			"fi\0"						\
-	"prog_uzImage_net="						\
-			"mw.b 0xa0000000 0xff 0x100000; "		\
-			"if	 bootp 0xa0000000 uzImage; "		\
-			"then "						\
-				"protect off 0x40000 0xfffff; "		\
-				"erase 0x40000 0xfffff; "		\
-				"cp.b 0xa0000000 0x40000 0x100000; "	\
-			"fi\0"						\
-	"prog_jffs_net="						\
-			"mw.b 0xa0000000 0xff 0x1e00000; "		\
-			"if	 bootp 0xa0000000 root.jffs; "		\
-			"then "						\
-				"protect off 0x140000 0x1f3ffff; "	\
-				"erase 0x140000 0x1f3ffff; "		\
-				"cp.b 0xa0000000 0x140000 0x1e00000; "	\
-			"fi\0"
-
-
-/*	"erase_env="			*/
-/*			"protect off"	*/
-
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER		1
-
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
-#else
-#endif
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_DEVICE_NULLDEV	1
-
-#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0xa0800000	/* default load address */
-
-#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
-
-#define RTC	1				/* enable 32KHz osc */
-
-#ifdef CONFIG_MMC
-#define	CONFIG_GENERIC_MMC
-#define	CONFIG_PXA_MMC_GENERIC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE		0xF0000000
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE		0xa0000000
-#define CONFIG_SYS_DRAM_SIZE		0x04000000
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800
-
-/*
- * GPIO settings
- */
-
-#define CONFIG_SYS_GAFR0_L_VAL	0x80001005
-#define CONFIG_SYS_GAFR0_U_VAL	0xa5128012
-#define CONFIG_SYS_GAFR1_L_VAL	0x699a9558
-#define CONFIG_SYS_GAFR1_U_VAL	0xaaa5aa6a
-#define CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL	0x2
-#define CONFIG_SYS_GPCR0_VAL	0x1800400
-#define CONFIG_SYS_GPCR1_VAL	0x0
-#define CONFIG_SYS_GPCR2_VAL	0x0
-#define CONFIG_SYS_GPDR0_VAL	0xc1818440
-#define CONFIG_SYS_GPDR1_VAL	0xfcffab82
-#define CONFIG_SYS_GPDR2_VAL	0x1ffff
-#define CONFIG_SYS_GPSR0_VAL	0x8000
-#define CONFIG_SYS_GPSR1_VAL	0x3f0002
-#define CONFIG_SYS_GPSR2_VAL	0x1c000
-
-#define CONFIG_SYS_PSSR_VAL		0x20
-
-#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
-#define	CONFIG_SYS_CKEN			0x0
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL		0x29DCA4D2
-#define CONFIG_SYS_MSC1_VAL		0x43AC494C
-#define CONFIG_SYS_MSC2_VAL		0x39D449D4
-#define CONFIG_SYS_MDCNFG_VAL		0x090009C9
-#define CONFIG_SYS_MDREFR_VAL		0x0085C017
-#define CONFIG_SYS_MDMRS_VAL		0x00220022
-#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
-#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL		0x00000003
-#define CONFIG_SYS_MCMEM0_VAL		0x00014405
-#define CONFIG_SYS_MCMEM1_VAL		0x00014405
-#define CONFIG_SYS_MCATT0_VAL		0x00014405
-#define CONFIG_SYS_MCATT1_VAL		0x00014405
-#define CONFIG_SYS_MCIO0_VAL		0x00014405
-#define CONFIG_SYS_MCIO1_VAL		0x00014405
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER	1
-
-#define CONFIG_SYS_MONITOR_BASE	0
-#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* put cfg at end of flash for now */
-#define CONFIG_ENV_IS_IN_FLASH	1
- /* Addr of Environment Sector	*/
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
-#define CONFIG_ENV_SIZE		PHYS_FLASH_SECT_SIZE	/* Total Size of Environment Sector	*/
-#define	CONFIG_ENV_SECT_SIZE	(PHYS_FLASH_SECT_SIZE / 16)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
deleted file mode 100644
index 0199190eb8..0000000000
--- a/include/configs/zipitz2.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Aeronix Zipit Z2 configuration file
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
-#define	CONFIG_ZIPITZ2		1	/* Zipit Z2 board */
-#define	CONFIG_SYS_TEXT_BASE	0x0
-
-#undef	CONFIG_BOARD_LATE_INIT
-#undef	CONFIG_SKIP_LOWLEVEL_INIT
-#define	CONFIG_PREBOOT
-
-/*
- * Environment settings
- */
-#define	CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_ADDR			0x40000
-#define CONFIG_ENV_SIZE			0x20000
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define	CONFIG_ARCH_CPU_INIT
-
-#define	CONFIG_BOOTCOMMAND						\
-	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
-	"then "								\
-		"source 0xa0000000; "					\
-	"else "								\
-		"bootm 0x60000; "					\
-	"fi; "
-#define	CONFIG_BOOTARGS							\
-	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
-#define	CONFIG_TIMESTAMP
-#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
-#define	CONFIG_CMDLINE_TAG
-#define	CONFIG_SETUP_MEMORY_TAGS
-#define	CONFIG_SYS_TEXT_BASE		0x0
-#define	CONFIG_LZMA			/* LZMA compression support */
-
-/*
- * Serial Console Configuration
- * STUART - the lower serial port on Colibri board
- */
-#define	CONFIG_PXA_SERIAL
-#define	CONFIG_STUART			1
-#define CONFIG_CONS_INDEX		2
-#define	CONFIG_BAUDRATE			115200
-
-/*
- * Bootloader Components Configuration
- */
-#define	CONFIG_CMD_ENV
-#define	CONFIG_CMD_MMC
-#define	CONFIG_CMD_SPI
-
-/*
- * MMC Card Configuration
- */
-#ifdef	CONFIG_CMD_MMC
-#define	CONFIG_MMC
-#define	CONFIG_GENERIC_MMC
-#define	CONFIG_PXA_MMC_GENERIC
-#define	CONFIG_SYS_MMC_BASE		0xF0000000
-#define	CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define	CONFIG_DOS_PARTITION
-#endif
-
-/*
- * SPI and LCD
- */
-#ifdef	CONFIG_CMD_SPI
-#define	CONFIG_SOFT_SPI
-#define	CONFIG_LCD
-#define	CONFIG_PXA_LCD
-#define	CONFIG_LMS283GF05
-#define	CONFIG_VIDEO_LOGO
-#define	CONFIG_CMD_BMP
-#define	CONFIG_SPLASH_SCREEN
-#define	CONFIG_SPLASH_SCREEN_ALIGN
-#define	CONFIG_VIDEO_BMP_GZIP
-#define	CONFIG_VIDEO_BMP_RLE8
-#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
-
-#define	SPI_DELAY	udelay(10)
-#define	SPI_SDA(val)	zipitz2_spi_sda(val)
-#define	SPI_SCL(val)	zipitz2_spi_scl(val)
-#define	SPI_READ	zipitz2_spi_read()
-#ifndef	__ASSEMBLY__
-void zipitz2_spi_sda(int);
-void zipitz2_spi_scl(int);
-unsigned char zipitz2_spi_read(void);
-#endif
-#endif
-
-/*
- * KGDB
- */
-#ifdef	CONFIG_CMD_KGDB
-#define	CONFIG_KGDB_BAUDRATE		230400		/* speed to run kgdb serial port */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define	CONFIG_SYS_HUSH_PARSER		1
-
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
-#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define	CONFIG_SYS_DEVICE_NULLDEV	1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED		0x190		/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
-
-/*
- * SRAM Map
- */
-#define	PHYS_SRAM			0x5c000000	/* SRAM Bank #1 */
-#define	PHYS_SRAM_SIZE			0x00040000	/* 256k */
-
-/*
- * DRAM Map
- */
-#define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
-#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
-#define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */
-
-#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
-#define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
-
-#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
-
-/*
- * NOR FLASH
- */
-#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
-#define PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
-#define PHYS_FLASH_SECT_SIZE		0x00010000	/* 64 KB sectors */
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER		1
-#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
-
-#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT	240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL	0x02000140
-#define CONFIG_SYS_GAFR0_U_VAL	0x59188000
-#define CONFIG_SYS_GAFR1_L_VAL	0x63900002
-#define CONFIG_SYS_GAFR1_U_VAL	0xaaa03950
-#define CONFIG_SYS_GAFR2_L_VAL	0x0aaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL	0x29000308
-#define CONFIG_SYS_GAFR3_L_VAL	0x54000000
-#define CONFIG_SYS_GAFR3_U_VAL	0x000000d5
-#define CONFIG_SYS_GPCR0_VAL	0x00000000
-#define CONFIG_SYS_GPCR1_VAL	0x00000020
-#define CONFIG_SYS_GPCR2_VAL	0x00000000
-#define CONFIG_SYS_GPCR3_VAL	0x00000000
-#define CONFIG_SYS_GPDR0_VAL	0xdafcee00
-#define CONFIG_SYS_GPDR1_VAL	0xffa3aaab
-#define CONFIG_SYS_GPDR2_VAL	0x8fe9ffff
-#define CONFIG_SYS_GPDR3_VAL	0x001b1f8a
-#define CONFIG_SYS_GPSR0_VAL	0x06080400
-#define CONFIG_SYS_GPSR1_VAL	0x007f0000
-#define CONFIG_SYS_GPSR2_VAL	0x032a0000
-#define CONFIG_SYS_GPSR3_VAL	0x00000180
-
-#define CONFIG_SYS_PSSR_VAL	0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN		0x00511220
-#define CONFIG_SYS_CCCR		0x00000190
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL	0x2ffc38f8
-#define CONFIG_SYS_MSC1_VAL	0x0000ccd1
-#define CONFIG_SYS_MSC2_VAL	0x0000b884
-#define CONFIG_SYS_MDCNFG_VAL	0x08000ba9
-#define CONFIG_SYS_MDREFR_VAL	0x2011a01e
-#define CONFIG_SYS_MDMRS_VAL	0x00000000
-#define CONFIG_SYS_FLYCNFG_VAL	0x00010001
-#define CONFIG_SYS_SXCNFG_VAL	0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL	0x00000001
-#define CONFIG_SYS_MCMEM0_VAL	0x00014307
-#define CONFIG_SYS_MCMEM1_VAL	0x00014307
-#define CONFIG_SYS_MCATT0_VAL	0x0001c787
-#define CONFIG_SYS_MCATT1_VAL	0x0001c787
-#define CONFIG_SYS_MCIO0_VAL	0x0001430f
-#define CONFIG_SYS_MCIO1_VAL	0x0001430f
-
-#endif	/* __CONFIG_H */