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authorBartlomiej Sieka <tur@semihalf.com>2007-01-23 13:25:22 +0100
committerBartlomiej Sieka <tur@semihalf.com>2007-01-23 13:25:22 +0100
commit363d1d8f9c99b63daef81f5985cab3fc00edde5c (patch)
tree80d3b9a28cecec05c92c2e3d12c4ab9eb4da6dff
parentc84bad0ef60e7055ab0bd49b93069509cecc382a (diff)
downloadblackbird-obmc-uboot-363d1d8f9c99b63daef81f5985cab3fc00edde5c.tar.gz
blackbird-obmc-uboot-363d1d8f9c99b63daef81f5985cab3fc00edde5c.zip
[ColdFire MCF5271 family] Add CPU detection based on the value of Chip
Identification Register (CIR).
-rw-r--r--cpu/mcf52x2/cpu.c34
-rw-r--r--include/asm-m68k/m5271.h6
2 files changed, 39 insertions, 1 deletions
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index aa6b2bd670..ce59d39cfa 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -49,11 +49,43 @@
#endif
#ifdef CONFIG_M5271
+/*
+ * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
+ * determine which one we are running on, based on the Chip Identification
+ * Register (CIR).
+ */
int checkcpu (void)
{
char buf[32];
+ unsigned short cir; /* Chip Identification Register */
+ unsigned short pin; /* Part identification number */
+ unsigned char prn; /* Part revision number */
+ char *cpu_model;
+
+ cir = mbar_readShort(MCF_CCM_CIR);
+ pin = cir >> MCF_CCM_CIR_PIN_LEN;
+ prn = cir & MCF_CCM_CIR_PRN_MASK;
+
+ switch (pin) {
+ case MCF_CCM_CIR_PIN_MCF5270:
+ cpu_model = "5270";
+ break;
+ case MCF_CCM_CIR_PIN_MCF5271:
+ cpu_model = "5271";
+ break;
+ default:
+ cpu_model = NULL;
+ break;
+ }
+
+ if (cpu_model)
+ printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
+ cpu_model, prn, strmhz(buf, CFG_CLK));
+ else
+ printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
+ " (PIN: 0x%x) rev. %hu, at %s MHz\n",
+ pin, prn, strmhz(buf, CFG_CLK));
- printf ("CPU: Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK));
return 0;
}
diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index 765414fdc3..e0f02cf7fd 100644
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -57,6 +57,12 @@
#define MCF_GPIO_PAR_FECI2C 0x100047
#define MCF_GPIO_PAR_UART 0x100048
+#define MCF_CCM_CIR 0x11000A
+#define MCF_CCM_CIR_PRN_MASK 0x3F
+#define MCF_CCM_CIR_PIN_LEN 6
+#define MCF_CCM_CIR_PIN_MCF5270 0x2e
+#define MCF_CCM_CIR_PIN_MCF5271 0x80
+
#define MCF_GPIO_AD_ADDR23 0x80
#define MCF_GPIO_AD_ADDR22 0x40
#define MCF_GPIO_AD_ADDR21 0x20
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