summaryrefslogtreecommitdiffstats
path: root/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
blob: 468d1abaf0eee1bea6d0ef4865ed998e4425bd1a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
/*
 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/reset.h>

#include "ccu_common.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_reset.h"

#include "ccu-sun8i-de2.h"

static SUNXI_CCU_GATE(bus_mixer0_clk,	"bus-mixer0",	"bus-de",
		      0x04, BIT(0), 0);
static SUNXI_CCU_GATE(bus_mixer1_clk,	"bus-mixer1",	"bus-de",
		      0x04, BIT(1), 0);
static SUNXI_CCU_GATE(bus_wb_clk,	"bus-wb",	"bus-de",
		      0x04, BIT(2), 0);

static SUNXI_CCU_GATE(mixer0_clk,	"mixer0",	"mixer0-div",
		      0x00, BIT(0), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(mixer1_clk,	"mixer1",	"mixer1-div",
		      0x00, BIT(1), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(wb_clk,		"wb",		"wb-div",
		      0x00, BIT(2), CLK_SET_RATE_PARENT);

static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
		   CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
		   CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
		   CLK_SET_RATE_PARENT);

static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
		   CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
		   CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
		   CLK_SET_RATE_PARENT);

static struct ccu_common *sun8i_a83t_de2_clks[] = {
	&mixer0_clk.common,
	&mixer1_clk.common,
	&wb_clk.common,

	&bus_mixer0_clk.common,
	&bus_mixer1_clk.common,
	&bus_wb_clk.common,

	&mixer0_div_a83_clk.common,
	&mixer1_div_a83_clk.common,
	&wb_div_a83_clk.common,
};

static struct ccu_common *sun8i_h3_de2_clks[] = {
	&mixer0_clk.common,
	&mixer1_clk.common,
	&wb_clk.common,

	&bus_mixer0_clk.common,
	&bus_mixer1_clk.common,
	&bus_wb_clk.common,

	&mixer0_div_clk.common,
	&mixer1_div_clk.common,
	&wb_div_clk.common,
};

static struct ccu_common *sun8i_v3s_de2_clks[] = {
	&mixer0_clk.common,
	&wb_clk.common,

	&bus_mixer0_clk.common,
	&bus_wb_clk.common,

	&mixer0_div_clk.common,
	&wb_div_clk.common,
};

static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
	.hws	= {
		[CLK_MIXER0]		= &mixer0_clk.common.hw,
		[CLK_MIXER1]		= &mixer1_clk.common.hw,
		[CLK_WB]		= &wb_clk.common.hw,

		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,

		[CLK_MIXER0_DIV]	= &mixer0_div_a83_clk.common.hw,
		[CLK_MIXER1_DIV]	= &mixer1_div_a83_clk.common.hw,
		[CLK_WB_DIV]		= &wb_div_a83_clk.common.hw,
	},
	.num	= CLK_NUMBER,
};

static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
	.hws	= {
		[CLK_MIXER0]		= &mixer0_clk.common.hw,
		[CLK_MIXER1]		= &mixer1_clk.common.hw,
		[CLK_WB]		= &wb_clk.common.hw,

		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,

		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
		[CLK_MIXER1_DIV]	= &mixer1_div_clk.common.hw,
		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
	},
	.num	= CLK_NUMBER,
};

static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
	.hws	= {
		[CLK_MIXER0]		= &mixer0_clk.common.hw,
		[CLK_WB]		= &wb_clk.common.hw,

		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,

		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
	},
	.num	= CLK_NUMBER,
};

static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
	[RST_MIXER0]	= { 0x08, BIT(0) },
	/*
	 * For A83T, H3 and R40, mixer1 reset line is shared with wb, so
	 * only RST_WB is exported here.
	 * For V3s there's just no mixer1, so it also shares this struct.
	 */
	[RST_WB]	= { 0x08, BIT(2) },
};

static struct ccu_reset_map sun50i_a64_de2_resets[] = {
	[RST_MIXER0]	= { 0x08, BIT(0) },
	[RST_MIXER1]	= { 0x08, BIT(1) },
	[RST_WB]	= { 0x08, BIT(2) },
};

static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
	.ccu_clks	= sun8i_a83t_de2_clks,
	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_de2_clks),

	.hw_clks	= &sun8i_a83t_de2_hw_clks,

	.resets		= sun8i_a83t_de2_resets,
	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
};

static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
	.ccu_clks	= sun8i_h3_de2_clks,
	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),

	.hw_clks	= &sun8i_h3_de2_hw_clks,

	.resets		= sun8i_a83t_de2_resets,
	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
};

static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
	.ccu_clks	= sun8i_h3_de2_clks,
	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),

	.hw_clks	= &sun8i_h3_de2_hw_clks,

	.resets		= sun50i_a64_de2_resets,
	.num_resets	= ARRAY_SIZE(sun50i_a64_de2_resets),
};

static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
	.ccu_clks	= sun8i_v3s_de2_clks,
	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_de2_clks),

	.hw_clks	= &sun8i_v3s_de2_hw_clks,

	.resets		= sun8i_a83t_de2_resets,
	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
};

static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct clk *bus_clk, *mod_clk;
	struct reset_control *rstc;
	void __iomem *reg;
	const struct sunxi_ccu_desc *ccu_desc;
	int ret;

	ccu_desc = of_device_get_match_data(&pdev->dev);
	if (!ccu_desc)
		return -EINVAL;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(reg))
		return PTR_ERR(reg);

	bus_clk = devm_clk_get(&pdev->dev, "bus");
	if (IS_ERR(bus_clk)) {
		ret = PTR_ERR(bus_clk);
		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
		return ret;
	}

	mod_clk = devm_clk_get(&pdev->dev, "mod");
	if (IS_ERR(mod_clk)) {
		ret = PTR_ERR(mod_clk);
		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev, "Couldn't get mod clk: %d\n", ret);
		return ret;
	}

	rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	if (IS_ERR(rstc)) {
		ret = PTR_ERR(rstc);
		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev,
				"Couldn't get reset control: %d\n", ret);
		return ret;
	}

	/* The clocks need to be enabled for us to access the registers */
	ret = clk_prepare_enable(bus_clk);
	if (ret) {
		dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare_enable(mod_clk);
	if (ret) {
		dev_err(&pdev->dev, "Couldn't enable mod clk: %d\n", ret);
		goto err_disable_bus_clk;
	}

	/* The reset control needs to be asserted for the controls to work */
	ret = reset_control_deassert(rstc);
	if (ret) {
		dev_err(&pdev->dev,
			"Couldn't deassert reset control: %d\n", ret);
		goto err_disable_mod_clk;
	}

	ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc);
	if (ret)
		goto err_assert_reset;

	return 0;

err_assert_reset:
	reset_control_assert(rstc);
err_disable_mod_clk:
	clk_disable_unprepare(mod_clk);
err_disable_bus_clk:
	clk_disable_unprepare(bus_clk);
	return ret;
}

static const struct of_device_id sunxi_de2_clk_ids[] = {
	{
		.compatible = "allwinner,sun8i-a83t-de2-clk",
		.data = &sun8i_a83t_de2_clk_desc,
	},
	{
		.compatible = "allwinner,sun8i-h3-de2-clk",
		.data = &sun8i_h3_de2_clk_desc,
	},
	{
		.compatible = "allwinner,sun8i-v3s-de2-clk",
		.data = &sun8i_v3s_de2_clk_desc,
	},
	{
		.compatible = "allwinner,sun50i-h5-de2-clk",
		.data = &sun50i_a64_de2_clk_desc,
	},
	/*
	 * The Allwinner A64 SoC needs some bit to be poke in syscon to make
	 * DE2 really working.
	 * So there's currently no A64 compatible here.
	 * H5 shares the same reset line with A64, so here H5 is using the
	 * clock description of A64.
	 */
	{ }
};

static struct platform_driver sunxi_de2_clk_driver = {
	.probe	= sunxi_de2_clk_probe,
	.driver	= {
		.name	= "sunxi-de2-clks",
		.of_match_table	= sunxi_de2_clk_ids,
	},
};
builtin_platform_driver(sunxi_de2_clk_driver);
OpenPOWER on IntegriCloud