From 778e2ac5970e445f8c6b7d8aa597ac162afe270a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Feb 2006 17:04:20 +0000 Subject: [MIPS] Fix build error on processors that don's support copy-on-write. Signed-off-by: Ralf Baechle --- include/asm-mips/io.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'include') diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 5a4c8a54b8f4..8c011aa61afa 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -282,6 +282,24 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, #define ioremap_nocache(offset, size) \ __ioremap_mode((offset), (size), _CACHE_UNCACHED) +/* + * ioremap_cachable - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap_nocache performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + * + * This version of ioremap ensures that the memory is marked cachable by + * the CPU. Also enables full write-combining. Useful for some + * memory-like regions on I/O busses. + */ +#define ioremap_cachable(offset, size) \ + __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT) + /* * These two are MIPS specific ioremap variant. ioremap_cacheable_cow * requests a cachable mapping, ioremap_uncached_accelerated requests a -- cgit v1.2.1