From 3ace822ad4b255eff7f56d2f452f7a8409b29b6d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 May 2018 05:39:51 +0200 Subject: serial: 8250: Add missing rxtrig_bytes on Altera 16550 UART The Altera 16550 UART core supports FCR Rx Trigger Level setting, but the port definition in the driver is missing the rxtrig_bytes array specifying the trigger levels. Add the array to make the Rx Trigger Level setting available on this type of 16550 UART. Signed-off-by: Marek Vasut Cc: Thor Thayer Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_port.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 8fbd5fbeb318..cf541aab2bd0 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -243,6 +243,7 @@ static const struct serial8250_config uart_config[] = { .fifo_size = 32, .tx_loadsz = 32, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .rxtrig_bytes = {1, 8, 16, 30}, .flags = UART_CAP_FIFO | UART_CAP_AFE, }, [PORT_ALTR_16550_F64] = { @@ -250,6 +251,7 @@ static const struct serial8250_config uart_config[] = { .fifo_size = 64, .tx_loadsz = 64, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .rxtrig_bytes = {1, 16, 32, 62}, .flags = UART_CAP_FIFO | UART_CAP_AFE, }, [PORT_ALTR_16550_F128] = { @@ -257,6 +259,7 @@ static const struct serial8250_config uart_config[] = { .fifo_size = 128, .tx_loadsz = 128, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .rxtrig_bytes = {1, 32, 64, 126}, .flags = UART_CAP_FIFO | UART_CAP_AFE, }, /* -- cgit v1.2.1