From d660030061dd7e20ad18557368188d9c1002ec71 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 21 Jun 2012 21:40:37 -0600 Subject: W1: OMAP HDQ1W: allow driver to be built on all OMAP2+ Allow the OMAP HDQ1W driver to be built for all OMAP2+ SoCs by adjusting KConfig dependencies. The previous dependency required either SOC_OMAP2430 or ARCH_OMAP3 to be set, but the HDQ IP block is present on OMAP2420 and OMAP44xx SoCs. The driver was still selectable on multi-OMAP kernel configurations, however; so the previous prohibition was rather pointless. Signed-off-by: Paul Walmsley Cc: Evgeniy Polyakov Acked-by: Evgeniy Polyakov --- drivers/w1/masters/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/w1') diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig index 979d6eed9a0f..5ceb1cd50195 100644 --- a/drivers/w1/masters/Kconfig +++ b/drivers/w1/masters/Kconfig @@ -60,7 +60,7 @@ config W1_MASTER_GPIO config HDQ_MASTER_OMAP tristate "OMAP HDQ driver" - depends on SOC_OMAP2430 || ARCH_OMAP3 + depends on ARCH_OMAP2PLUS help Say Y here if you want support for the 1-wire or HDQ Interface on an OMAP processor. -- cgit v1.2.1 From 2acd089471d93373e051c6b1f9f9e0d9e51a76bc Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 21 Jun 2012 21:40:37 -0600 Subject: W1: OMAP HDQ1W: use 32-bit register accesses HDQ/1-wire registers are 32 bits long, even if the register contents fit into 8 bits, so accesses must be 32-bit aligned. Evidently the OMAP2/3 interconnects allowed the driver to get away with 8 bit accesses, but the OMAP4 puts a stop to that: [ 1.488800] Driver for 1-wire Dallas network protocol. [ 1.495025] Bad mode in data abort handler detected [ 1.500122] Internal error: Oops - bad mode: 0 [#1] SMP [ 1.505615] Modules linked in: [ 1.508819] CPU: 0 Not tainted (3.3.0-rc1-00008-g45030e9 #992) [ 1.515289] PC is at 0xffff0018 [ 1.518615] LR is at omap_hdq_probe+0xd4/0x2cc The OMAP4430 ES2 Rev X TRM does warn about this restriction in section 23.2.6.2 "HDQ/1-Wire Registers". Fixes the crash on OMAP4430 ES2 Pandaboard. Tested also on OMAP34xx and OMAP2420; it seems to work fine on those chips, although due to the lack of boards with HDQ/1-wire devices here, a more indepth test was not possible. Signed-off-by: Paul Walmsley Cc: NeilBrown Cc: Evgeniy Polyakov Acked-by: Evgeniy Polyakov --- drivers/w1/masters/omap_hdq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/w1') diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index 5ef385bfed18..344db9c5ab88 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c @@ -102,20 +102,20 @@ static struct w1_bus_master omap_w1_master = { /* HDQ register I/O routines */ static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset) { - return __raw_readb(hdq_data->hdq_base + offset); + return __raw_readl(hdq_data->hdq_base + offset); } static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val) { - __raw_writeb(val, hdq_data->hdq_base + offset); + __raw_writel(val, hdq_data->hdq_base + offset); } static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset, u8 val, u8 mask) { - u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask) + u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask) | (val & mask); - __raw_writeb(new_val, hdq_data->hdq_base + offset); + __raw_writel(new_val, hdq_data->hdq_base + offset); return new_val; } -- cgit v1.2.1 From c354a86484b61e32100eb94c1f3f0aa512958cee Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 21 Jun 2012 21:40:40 -0600 Subject: W1: OMAP HDQ1W: use runtime PM Convert the OMAP HDQ driver to use runtime PM. Compile- and boot-tested, but not tested in actual use. Signed-off-by: Paul Walmsley Cc: NeilBrown Cc: Evgeniy Polyakov Acked-by: Evgeniy Polyakov Tested-by: NeilBrown --- drivers/w1/masters/omap_hdq.c | 78 ++++++++----------------------------------- 1 file changed, 13 insertions(+), 65 deletions(-) (limited to 'drivers/w1') diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index 344db9c5ab88..291897c881be 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c @@ -1,7 +1,7 @@ /* * drivers/w1/masters/omap_hdq.c * - * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007,2012 Texas Instruments, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -14,9 +14,9 @@ #include #include #include -#include #include #include +#include #include #include @@ -61,8 +61,6 @@ struct hdq_data { /* lock status update */ struct mutex hdq_mutex; int hdq_usecount; - struct clk *hdq_ick; - struct clk *hdq_fck; u8 hdq_irqstatus; /* device lock */ spinlock_t hdq_spinlock; @@ -419,17 +417,8 @@ static int omap_hdq_get(struct hdq_data *hdq_data) hdq_data->hdq_usecount++; try_module_get(THIS_MODULE); if (1 == hdq_data->hdq_usecount) { - if (clk_enable(hdq_data->hdq_ick)) { - dev_dbg(hdq_data->dev, "Can not enable ick\n"); - ret = -ENODEV; - goto clk_err; - } - if (clk_enable(hdq_data->hdq_fck)) { - dev_dbg(hdq_data->dev, "Can not enable fck\n"); - clk_disable(hdq_data->hdq_ick); - ret = -ENODEV; - goto clk_err; - } + + pm_runtime_get_sync(hdq_data->dev); /* make sure HDQ is out of reset */ if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) & @@ -450,9 +439,6 @@ static int omap_hdq_get(struct hdq_data *hdq_data) } } -clk_err: - clk_put(hdq_data->hdq_ick); - clk_put(hdq_data->hdq_fck); out: mutex_unlock(&hdq_data->hdq_mutex); rtn: @@ -475,10 +461,8 @@ static int omap_hdq_put(struct hdq_data *hdq_data) } else { hdq_data->hdq_usecount--; module_put(THIS_MODULE); - if (0 == hdq_data->hdq_usecount) { - clk_disable(hdq_data->hdq_ick); - clk_disable(hdq_data->hdq_fck); - } + if (0 == hdq_data->hdq_usecount) + pm_runtime_put_sync(hdq_data->dev); } mutex_unlock(&hdq_data->hdq_mutex); @@ -591,35 +575,11 @@ static int __devinit omap_hdq_probe(struct platform_device *pdev) goto err_ioremap; } - /* get interface & functional clock objects */ - hdq_data->hdq_ick = clk_get(&pdev->dev, "ick"); - if (IS_ERR(hdq_data->hdq_ick)) { - dev_dbg(&pdev->dev, "Can't get HDQ ick clock object\n"); - ret = PTR_ERR(hdq_data->hdq_ick); - goto err_ick; - } - - hdq_data->hdq_fck = clk_get(&pdev->dev, "fck"); - if (IS_ERR(hdq_data->hdq_fck)) { - dev_dbg(&pdev->dev, "Can't get HDQ fck clock object\n"); - ret = PTR_ERR(hdq_data->hdq_fck); - goto err_fck; - } - hdq_data->hdq_usecount = 0; mutex_init(&hdq_data->hdq_mutex); - if (clk_enable(hdq_data->hdq_ick)) { - dev_dbg(&pdev->dev, "Can not enable ick\n"); - ret = -ENODEV; - goto err_intfclk; - } - - if (clk_enable(hdq_data->hdq_fck)) { - dev_dbg(&pdev->dev, "Can not enable fck\n"); - ret = -ENODEV; - goto err_fnclk; - } + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION); dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n", @@ -641,9 +601,7 @@ static int __devinit omap_hdq_probe(struct platform_device *pdev) omap_hdq_break(hdq_data); - /* don't clock the HDQ until it is needed */ - clk_disable(hdq_data->hdq_ick); - clk_disable(hdq_data->hdq_fck); + pm_runtime_put_sync(&pdev->dev); omap_w1_master.data = hdq_data; @@ -655,20 +613,11 @@ static int __devinit omap_hdq_probe(struct platform_device *pdev) return 0; -err_w1: err_irq: - clk_disable(hdq_data->hdq_fck); - -err_fnclk: - clk_disable(hdq_data->hdq_ick); - -err_intfclk: - clk_put(hdq_data->hdq_fck); - -err_fck: - clk_put(hdq_data->hdq_ick); + pm_runtime_put_sync(&pdev->dev); +err_w1: + pm_runtime_disable(&pdev->dev); -err_ick: iounmap(hdq_data->hdq_base); err_ioremap: @@ -696,8 +645,7 @@ static int omap_hdq_remove(struct platform_device *pdev) mutex_unlock(&hdq_data->hdq_mutex); /* remove module dependency */ - clk_put(hdq_data->hdq_ick); - clk_put(hdq_data->hdq_fck); + pm_runtime_disable(&pdev->dev); free_irq(INT_24XX_HDQ_IRQ, hdq_data); platform_set_drvdata(pdev, NULL); iounmap(hdq_data->hdq_base); -- cgit v1.2.1