From e1993ed6420afd4421336d75e73641f75da87a7f Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Tue, 19 Oct 2010 18:03:27 +0800 Subject: spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode In the TX_ONLY transfer, the SPI controller also receives data simultaneously and saves them in the rx register. After the TX_ONLY transfer, the rx register will hold the random data received during the last tx transaction. If the direct following transfer is RX_ONLY, this random data has the possibility to affect this transfer like this: When the SPI controller is changed from TX_ONLY to RX_ONLY, the random data makes the rx register full immediately and triggers a dummy write automatically(in SPI RX_ONLY transfers, we need a dummy write to trigger the first transaction). So the first data received in the RX_ONLY transfer will be that random data instead of something meaningful. We can avoid this by inserting a Disable/Re-enable toggle of the channel after the TX_ONLY transfer, since it purges the rx register. Signed-off-by: Jason Wang Tested-by: Grazvydas Ignotas Acked-by: Tony Lindgren Signed-off-by: Grant Likely --- drivers/spi/omap2_mcspi.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/spi/omap2_mcspi.c') diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index d70392795055..27a3fa1f3bf4 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -626,6 +626,12 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) } else if (mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_EOT) < 0) dev_err(&spi->dev, "EOT timed out\n"); + + /* disable chan to purge rx datas received in TX_ONLY transfer, + * otherwise these rx datas will affect the direct following + * RX_ONLY transfer. + */ + omap2_mcspi_set_enable(spi, 0); } out: omap2_mcspi_set_enable(spi, 1); -- cgit v1.2.1