From 0fda65680e92545caea5be7805a7f0a617fb6c20 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 27 Feb 2015 15:12:35 +0000 Subject: drm/i915/skl: Update watermarks for Y tiling Display watermarks need different programming for different tiling modes. Set the relevant flag so this happens during the plane commit and add relevant data into a structure made available to the watermark computation code. v2: Pass in tiling info to sprite plane updates as well. v3: Rebased for plane handling changes. v4: Handle fb == NULL when plane is disabled. v5: Refactored for addfb2 interface. v6: Refactored for fb modifier changes. v7: Updated for atomic commit by only updating watermarks when tiling changes. v8: BSpec watermark calculation updates. v9: Restrict scope of y_tile_minimum variable. (Damien Lespiau) v10: Get fb from plane state otherwise we are working on old state. Signed-off-by: Tvrtko Ursulin Acked-by: Ander Conselvan de Oliveira Acked-by: Matt Roper Reviewed-by: Damien Lespiau (v9) Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sprite.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/drm/i915/intel_sprite.c') diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index bdb64fc14655..7051da7015d3 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1256,6 +1256,12 @@ finish: if (!intel_crtc->primary_enabled && !state->hides_primary) intel_crtc->atomic.post_enable_primary = true; + + /* Update watermarks on tiling changes. */ + if (!plane->state->fb || !state->base.fb || + plane->state->fb->modifier[0] != + state->base.fb->modifier[0]) + intel_crtc->atomic.update_wm = true; } return 0; -- cgit v1.2.3