From aa4747c00a2dd034c5fdf70ca73b1674ca15beb3 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 4 Nov 2016 20:35:46 +0800 Subject: drm/amdgpu: refine uvd_4.2 clock gate sequence. 1. partial revert commit 91db308d6e96. not set uvd bypass mode. 2. enable uvd cg before initialize uvd. 3. set uvd clock to default value 100MHz. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/ci_dpm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index bd690a21fdfa..fe42e2fb2622 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -4202,11 +4202,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) if (!gate) { /* turn the clocks on when decoding */ - ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); - if (ret) - return ret; - if (pi->caps_uvd_dpm || (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) pi->smc_state_table.UvdBootLevel = 0; @@ -4223,9 +4218,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) ret = ci_enable_uvd_dpm(adev, false); if (ret) return ret; - - ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); } return ret; -- cgit v1.2.3