From bdca21ecc252b5d390065de03d03c5a9df491025 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Sun, 14 Apr 2013 17:28:35 +1200 Subject: clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate. The case of PLL_TYPE_WM8750 in both these functions is missing a break statement causing a fall-through to the default: case. Insert the missing break statements. Signed-off-by: Tony Prisk Signed-off-by: Mike Turquette --- drivers/clk/clk-vt8500.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk/clk-vt8500.c') diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index b5538bba7a10..6bc82d1bfe78 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -488,6 +488,7 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate, case PLL_TYPE_WM8750: wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2); pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); + break; default: pr_err("%s: invalid pll type\n", __func__); return 0; @@ -523,6 +524,7 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, case PLL_TYPE_WM8750: wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); + break; default: round_rate = 0; } -- cgit v1.2.1