From 3f2bbf443e21584887f954328ceee8515d7691e7 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 19 Jun 2018 09:03:16 +0200 Subject: xtensa: use generic dma_noncoherent_ops Switch to the generic noncoherent direct mapping implementation. Signed-off-by: Christoph Hellwig Signed-off-by: Max Filippov --- arch/xtensa/include/asm/Kbuild | 1 + arch/xtensa/include/asm/dma-mapping.h | 26 -------------------------- 2 files changed, 1 insertion(+), 26 deletions(-) delete mode 100644 arch/xtensa/include/asm/dma-mapping.h (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/Kbuild b/arch/xtensa/include/asm/Kbuild index e5e1e61c538c..82c756431b49 100644 --- a/arch/xtensa/include/asm/Kbuild +++ b/arch/xtensa/include/asm/Kbuild @@ -3,6 +3,7 @@ generic-y += compat.h generic-y += device.h generic-y += div64.h generic-y += dma-contiguous.h +generic-y += dma-mapping.h generic-y += emergency-restart.h generic-y += exec.h generic-y += extable.h diff --git a/arch/xtensa/include/asm/dma-mapping.h b/arch/xtensa/include/asm/dma-mapping.h deleted file mode 100644 index 44098800dad7..000000000000 --- a/arch/xtensa/include/asm/dma-mapping.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 - 2005 Tensilica Inc. - * Copyright (C) 2015 Cadence Design Systems Inc. - */ - -#ifndef _XTENSA_DMA_MAPPING_H -#define _XTENSA_DMA_MAPPING_H - -#include -#include - -#include -#include - -extern const struct dma_map_ops xtensa_dma_map_ops; - -static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) -{ - return &xtensa_dma_map_ops; -} - -#endif /* _XTENSA_DMA_MAPPING_H */ -- cgit v1.2.1 From 2cc15e802b250a11ece57ea54f82993cf3430867 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 11 Jul 2018 14:33:41 -0700 Subject: xtensa: platform-specific handling of coherent memory Memory layout is not fixed for noMMU xtensa configurations. Platforms that need to use coherent DMA should implement platform_vaddr_* helpers that check address type (cached/uncached) and convert addresses between these types. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/kmem_layout.h | 6 ------ arch/xtensa/include/asm/pgtable.h | 8 ++++++++ arch/xtensa/include/asm/platform.h | 27 +++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 6 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/kmem_layout.h b/arch/xtensa/include/asm/kmem_layout.h index 2317c835a4db..9c12babc016c 100644 --- a/arch/xtensa/include/asm/kmem_layout.h +++ b/arch/xtensa/include/asm/kmem_layout.h @@ -63,12 +63,6 @@ #error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT #endif -#else - -#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) -#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) -#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) - #endif #ifndef CONFIG_KASAN diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h index 38802259978f..29cfe421cf41 100644 --- a/arch/xtensa/include/asm/pgtable.h +++ b/arch/xtensa/include/asm/pgtable.h @@ -66,6 +66,7 @@ #define FIRST_USER_ADDRESS 0UL #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) +#ifdef CONFIG_MMU /* * Virtual memory area. We keep a distance to other memory regions to be * on the safe side. We also use this area for cache aliasing. @@ -80,6 +81,13 @@ #define TLBTEMP_SIZE ICACHE_WAY_SIZE #endif +#else + +#define VMALLOC_START __XTENSA_UL_CONST(0) +#define VMALLOC_END __XTENSA_UL_CONST(0xffffffff) + +#endif + /* * For the Xtensa architecture, the PTE layout is as follows: * diff --git a/arch/xtensa/include/asm/platform.h b/arch/xtensa/include/asm/platform.h index f8fbef67bc5f..560483356a06 100644 --- a/arch/xtensa/include/asm/platform.h +++ b/arch/xtensa/include/asm/platform.h @@ -75,4 +75,31 @@ extern void platform_calibrate_ccount (void); */ void cpu_reset(void) __attribute__((noreturn)); +/* + * Memory caching is platform-dependent in noMMU xtensa configurations. + * The following set of functions should be implemented in platform code + * in order to enable coherent DMA memory operations when CONFIG_MMU is not + * enabled. Default implementations do nothing and issue a warning. + */ + +/* + * Check whether p points to a cached memory. + */ +bool platform_vaddr_cached(const void *p); + +/* + * Check whether p points to an uncached memory. + */ +bool platform_vaddr_uncached(const void *p); + +/* + * Return pointer to an uncached view of the cached sddress p. + */ +void *platform_vaddr_to_uncached(void *p); + +/* + * Return pointer to a cached view of the uncached sddress p. + */ +void *platform_vaddr_to_cached(void *p); + #endif /* _XTENSA_PLATFORM_H */ -- cgit v1.2.1 From be75de25251f7cf3e399ca1f584716a95510d24a Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Fri, 10 Aug 2018 20:43:48 -0700 Subject: xtensa: limit offsets in __loop_cache_{all,page} When building kernel for xtensa cores with big cache lines (e.g. 128 bytes or more) __loop_cache_all and __loop_cache_page may generate assembly instructions with immediate fields that are too big. This results in the following build errors: arch/xtensa/mm/misc.S: Assembler messages: arch/xtensa/mm/misc.S:464: Error: operand 2 of 'diwbi' has invalid value '256' arch/xtensa/mm/misc.S:464: Error: operand 2 of 'diwbi' has invalid value '384' arch/xtensa/kernel/head.S: Assembler messages: arch/xtensa/kernel/head.S:172: Error: operand 2 of 'diu' has invalid value '256' arch/xtensa/kernel/head.S:172: Error: operand 2 of 'diu' has invalid value '384' arch/xtensa/kernel/head.S:176: Error: operand 2 of 'iiu' has invalid value '256' arch/xtensa/kernel/head.S:176: Error: operand 2 of 'iiu' has invalid value '384' arch/xtensa/kernel/head.S:255: Error: operand 2 of 'diwb' has invalid value '256' arch/xtensa/kernel/head.S:255: Error: operand 2 of 'diwb' has invalid value '384' Add parameter max_immed to these macros and use it to limit values of immediate operands. Extract common code of these macros into the new macro __loop_cache_unroll. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov --- arch/xtensa/include/asm/cacheasm.h | 65 +++++++++++++++++++++++--------------- 1 file changed, 40 insertions(+), 25 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h index 2041abb10a23..2c73b4571226 100644 --- a/arch/xtensa/include/asm/cacheasm.h +++ b/arch/xtensa/include/asm/cacheasm.h @@ -31,16 +31,32 @@ * */ - .macro __loop_cache_all ar at insn size line_width - movi \ar, 0 + .macro __loop_cache_unroll ar at insn size line_width max_immed + + .if (1 << (\line_width)) > (\max_immed) + .set _reps, 1 + .elseif (2 << (\line_width)) > (\max_immed) + .set _reps, 2 + .else + .set _reps, 4 + .endif + + __loopi \ar, \at, \size, (_reps << (\line_width)) + .set _index, 0 + .rep _reps + \insn \ar, _index << (\line_width) + .set _index, _index + 1 + .endr + __endla \ar, \at, _reps << (\line_width) + + .endm + - __loopi \ar, \at, \size, (4 << (\line_width)) - \insn \ar, 0 << (\line_width) - \insn \ar, 1 << (\line_width) - \insn \ar, 2 << (\line_width) - \insn \ar, 3 << (\line_width) - __endla \ar, \at, 4 << (\line_width) + .macro __loop_cache_all ar at insn size line_width max_immed + + movi \ar, 0 + __loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed .endm @@ -57,14 +73,9 @@ .endm - .macro __loop_cache_page ar at insn line_width + .macro __loop_cache_page ar at insn line_width max_immed - __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) - \insn \ar, 0 << (\line_width) - \insn \ar, 1 << (\line_width) - \insn \ar, 2 << (\line_width) - \insn \ar, 3 << (\line_width) - __endla \ar, \at, 4 << (\line_width) + __loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed .endm @@ -72,7 +83,8 @@ .macro ___unlock_dcache_all ar at #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE - __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH + __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \ + XCHAL_DCACHE_LINEWIDTH 240 #endif .endm @@ -81,7 +93,8 @@ .macro ___unlock_icache_all ar at #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE - __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH + __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \ + XCHAL_ICACHE_LINEWIDTH 240 #endif .endm @@ -90,7 +103,8 @@ .macro ___flush_invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE - __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH + __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \ + XCHAL_DCACHE_LINEWIDTH 240 #endif .endm @@ -99,7 +113,8 @@ .macro ___flush_dcache_all ar at #if XCHAL_DCACHE_SIZE - __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH + __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \ + XCHAL_DCACHE_LINEWIDTH 240 #endif .endm @@ -109,7 +124,7 @@ #if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ - XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm @@ -119,7 +134,7 @@ #if XCHAL_ICACHE_SIZE __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ - XCHAL_ICACHE_LINEWIDTH + XCHAL_ICACHE_LINEWIDTH 1020 #endif .endm @@ -166,7 +181,7 @@ .macro ___flush_invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE - __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH + __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm @@ -175,7 +190,7 @@ .macro ___flush_dcache_page ar as #if XCHAL_DCACHE_SIZE - __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH + __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm @@ -184,7 +199,7 @@ .macro ___invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE - __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH + __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm @@ -193,7 +208,7 @@ .macro ___invalidate_icache_page ar as #if XCHAL_ICACHE_SIZE - __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH + __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020 #endif .endm -- cgit v1.2.1 From fec3259c9f747c039f90e99570540114c8d81a14 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Fri, 10 Aug 2018 22:21:22 -0700 Subject: xtensa: increase ranges in ___invalidate_{i,d}cache_all Cache invalidation macros use cache line size to iterate over invalidated cache lines, assuming that all cache ways are invalidated by single instruction, but xtensa ISA recommends to not assume that for future compatibility: In some implementations all ways at index Addry-1..z are invalidated regardless of the specified way, but for future compatibility this behavior should not be assumed. Iterate over all cache ways in ___invalidate_icache_all and ___invalidate_dcache_all. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov --- arch/xtensa/include/asm/cacheasm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h index 2c73b4571226..34545ecfdd6b 100644 --- a/arch/xtensa/include/asm/cacheasm.h +++ b/arch/xtensa/include/asm/cacheasm.h @@ -123,7 +123,7 @@ .macro ___invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE - __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ + __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 1020 #endif @@ -133,7 +133,7 @@ .macro ___invalidate_icache_all ar at #if XCHAL_ICACHE_SIZE - __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ + __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \ XCHAL_ICACHE_LINEWIDTH 1020 #endif -- cgit v1.2.1 From 7bb516ca5424e12b42124fab2906b6da9c81ba9c Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sun, 12 Aug 2018 06:01:40 -0700 Subject: xtensa: rework noMMU cache attributes initialization Marking default memory region as cached is not always sufficient and is not flexible. Allow specifying cache attributes for the whole memory address space with new config entry MEMMAP_CACHEATTR. Apply it after cache initialization. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/initialize_mmu.h | 42 ++++++++++++++++---------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h index 42410f253597..10e9852b2fb4 100644 --- a/arch/xtensa/include/asm/initialize_mmu.h +++ b/arch/xtensa/include/asm/initialize_mmu.h @@ -177,36 +177,36 @@ #endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY */ -#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \ - (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE) - /* Enable data and instruction cache in the DEFAULT_MEMORY region - * if the processor has DTLB and ITLB. - */ + .endm + + .macro initialize_cacheattr - movi a5, PLATFORM_DEFAULT_MEM_START | XCHAL_SPANNING_WAY +#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS +#if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU +#error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU. +#endif + + movi a5, XCHAL_SPANNING_WAY movi a6, ~_PAGE_ATTRIB_MASK - movi a7, CA_WRITEBACK + movi a4, CONFIG_MEMMAP_CACHEATTR movi a8, 0x20000000 - movi a9, PLATFORM_DEFAULT_MEM_SIZE - j 2f 1: - sub a9, a9, a8 -2: -#if XCHAL_DCACHE_SIZE rdtlb1 a3, a5 + xor a3, a3, a4 and a3, a3, a6 - or a3, a3, a7 + xor a3, a3, a4 wdtlb a3, a5 -#endif -#if XCHAL_ICACHE_SIZE - ritlb1 a4, a5 - and a4, a4, a6 - or a4, a4, a7 - witlb a4, a5 -#endif + ritlb1 a3, a5 + xor a3, a3, a4 + and a3, a3, a6 + xor a3, a3, a4 + witlb a3, a5 + add a5, a5, a8 - bltu a8, a9, 1b + srli a4, a4, 4 + bgeu a5, a8, 1b + isync #endif .endm -- cgit v1.2.1 From aea731c81f998af5e45654459bac24a1c808fb22 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 13 Aug 2018 16:45:54 -0700 Subject: xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START Drop PLATFORM_DEFAULT_MEM_START from the platform/hardware.h headers. Provide definition of CONFIG_DEFAULT_MEM_START always, allow changing it only in noMMU configurations when PLATFORM_WANT_DEFAULT_MEM is selected. Change prompt and description so that it's clear that it controls PAGE_OFFSET and PHYS_OFFSET. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/page.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/page.h b/arch/xtensa/include/asm/page.h index 5d69c11c01b8..09c56cba442e 100644 --- a/arch/xtensa/include/asm/page.h +++ b/arch/xtensa/include/asm/page.h @@ -14,7 +14,6 @@ #include #include #include -#include #include /* @@ -31,8 +30,8 @@ #define MAX_LOW_PFN (PHYS_PFN(XCHAL_KSEG_PADDR) + \ PHYS_PFN(XCHAL_KSEG_SIZE)) #else -#define PAGE_OFFSET PLATFORM_DEFAULT_MEM_START -#define PHYS_OFFSET PLATFORM_DEFAULT_MEM_START +#define PAGE_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL) +#define PHYS_OFFSET _AC(CONFIG_DEFAULT_MEM_START, UL) #define MAX_LOW_PFN PHYS_PFN(0xfffffffful) #endif -- cgit v1.2.1 From 994fa1c83d658f857dacf0512e8f7db246143d26 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 13 Aug 2018 18:11:38 -0700 Subject: xtensa: move PLATFORM_NR_IRQS to Kconfig Signed-off-by: Max Filippov --- arch/xtensa/include/asm/irq.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h index 19707db966f1..2270d93ab7e6 100644 --- a/arch/xtensa/include/asm/irq.h +++ b/arch/xtensa/include/asm/irq.h @@ -12,7 +12,6 @@ #define _XTENSA_IRQ_H #include -#include #include #ifdef CONFIG_VARIANT_IRQ_SWITCH @@ -25,7 +24,9 @@ static inline void variant_irq_disable(unsigned int irq) { } #ifndef VARIANT_NR_IRQS # define VARIANT_NR_IRQS 0 #endif -#ifndef PLATFORM_NR_IRQS +#ifdef CONFIG_PLATFORM_NR_IRQS +# define PLATFORM_NR_IRQS CONFIG_PLATFORM_NR_IRQS +#else # define PLATFORM_NR_IRQS 0 #endif #define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS -- cgit v1.2.1 From fc862ee9976f0490a20b2a2b8ae0c4fbeb7bbf13 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 13 Aug 2018 18:14:14 -0700 Subject: xtensa: drop unneeded platform/hardware.h headers platform/hardware.h no longer supply any information for processor.h, vectors.h, setup.c or vmlinux.lds.S, don't include it. This header is now empty in the platforms/iss, so remove it altogether. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/processor.h | 1 - arch/xtensa/include/asm/vectors.h | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h index 5b0027d4ecc0..e4ccb88b7996 100644 --- a/arch/xtensa/include/asm/processor.h +++ b/arch/xtensa/include/asm/processor.h @@ -11,7 +11,6 @@ #define _XTENSA_PROCESSOR_H #include -#include #include #include diff --git a/arch/xtensa/include/asm/vectors.h b/arch/xtensa/include/asm/vectors.h index 65d3da9db19b..7111280c8842 100644 --- a/arch/xtensa/include/asm/vectors.h +++ b/arch/xtensa/include/asm/vectors.h @@ -19,7 +19,6 @@ #define _XTENSA_VECTORS_H #include -#include #include #if XCHAL_HAVE_PTP_MMU -- cgit v1.2.1 From 8b5163eb988067093064ecb10265da27fd000cad Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 13 Aug 2018 18:21:08 -0700 Subject: xtensa: drop variant IRQ support If an xtensa core provides an additional IRQ controller it should be treated as a separate piece of hardware and be driven by an irqchip driver. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/irq.h | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'arch/xtensa/include') diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h index 2270d93ab7e6..6c6ed23e0c79 100644 --- a/arch/xtensa/include/asm/irq.h +++ b/arch/xtensa/include/asm/irq.h @@ -14,31 +14,15 @@ #include #include -#ifdef CONFIG_VARIANT_IRQ_SWITCH -#include -#else -static inline void variant_irq_enable(unsigned int irq) { } -static inline void variant_irq_disable(unsigned int irq) { } -#endif - -#ifndef VARIANT_NR_IRQS -# define VARIANT_NR_IRQS 0 -#endif #ifdef CONFIG_PLATFORM_NR_IRQS # define PLATFORM_NR_IRQS CONFIG_PLATFORM_NR_IRQS #else # define PLATFORM_NR_IRQS 0 #endif #define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS -#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS + 1) +#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS + 1) #define XTENSA_PIC_LINUX_IRQ(hwirq) ((hwirq) + 1) -#if VARIANT_NR_IRQS == 0 -static inline void variant_init_irq(void) { } -#else -void variant_init_irq(void) __init; -#endif - static __inline__ int irq_canonicalize(int irq) { return (irq); -- cgit v1.2.1