From b8f44ec2c05f9cfe1647173ac60c0cccb1118c91 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 5 Aug 2010 02:45:08 -0500 Subject: powerpc/fsl-pci: Fix MSI support on 83xx platforms The following commit broke 83xx because it assumed the 83xx platforms exposed the "IMMR" address in BAR0 like the 85xx/86xx/QoriQ devices do: commit 3da34aae03d498ee62f75aa7467de93cce3030fd Author: Kumar Gala Date: Tue May 12 15:51:56 2009 -0500 powerpc/fsl: Support unique MSI addresses per PCIe Root Complex However that is not true, so we have to search through the inbound window settings on 83xx to find which one matches the IMMR address to determine its PCI address. Reported-by: Ilya Yanok Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_msi.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch/powerpc/sysdev/fsl_msi.c') diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 87991d3abbab..20cdcd2b0eed 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -24,6 +24,7 @@ #include #include #include "fsl_msi.h" +#include "fsl_pci.h" LIST_HEAD(msi_head); @@ -125,13 +126,11 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, { struct fsl_msi *msi_data = fsl_msi_data; struct pci_controller *hose = pci_bus_to_host(pdev->bus); - u32 base = 0; + u64 base = fsl_pci_immrbar_base(hose); - pci_bus_read_config_dword(hose->bus, - PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); + msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base); + msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base); - msg->address_lo = msi_data->msi_addr_lo + base; - msg->address_hi = msi_data->msi_addr_hi; msg->data = hwirq; pr_debug("%s: allocated srs: %d, ibs: %d\n", -- cgit v1.2.1