From 1b432840d0a4740020e29ae7a00717ef8f44954b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 31 Oct 2008 14:24:29 +0100 Subject: MIPS: RB532: GPIO register offsets are relative to GPIOBASE This patch fixes the wrong use of GPIO register offsets in devices.c. To avoid further problems, use gpio_get_value to return the NAND status instead of our own expanded code. Also define the zero offset of the alternate function register to allow consistent access. Signed-off-by: Florian Fainelli Signed-off-by: Phil Sutter Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-rc32434/rb.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'arch/mips/include/asm/mach-rc32434') diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index 79e8ef67d0d3..f25a84916703 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -40,12 +40,14 @@ #define BTCS 0x010040 #define BTCOMPARE 0x010044 #define GPIOBASE 0x050000 -#define GPIOCFG 0x050004 -#define GPIOD 0x050008 -#define GPIOILEVEL 0x05000C -#define GPIOISTAT 0x050010 -#define GPIONMIEN 0x050014 -#define IMASK6 0x038038 +/* Offsets relative to GPIOBASE */ +#define GPIOFUNC 0x00 +#define GPIOCFG 0x04 +#define GPIOD 0x08 +#define GPIOILEVEL 0x0C +#define GPIOISTAT 0x10 +#define GPIONMIEN 0x14 +#define IMASK6 0x38 #define LO_WPX (1 << 0) #define LO_ALE (1 << 1) #define LO_CLE (1 << 2) -- cgit v1.2.1