From 74ddcdb868a84f4a9f65e33c1ca0d24e1134e53a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 21 Dec 2012 22:42:39 +0100 Subject: ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier PL310 errata work-arounds using .set_debug function are only needed on r3p0 and earlier, so check the rev and only set .set_debug on older revs. Avoiding debug register accesses fixes aborts on non-secure platforms like highbank. It is assumed that non-secure platforms needing these work-arounds have already implemented .set_debug with secure monitor calls. Signed-off-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 6911b8b2745c..05d577613b13 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -352,7 +352,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) /* Unmapped register. */ sync_reg_offset = L2X0_DUMMY_REG; #endif - outer_cache.set_debug = pl310_set_debug; + if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0) + outer_cache.set_debug = pl310_set_debug; break; case L2X0_CACHE_ID_PART_L210: ways = (aux >> 13) & 0xf; -- cgit v1.2.1 From 62e4d357aae0c7438c537bdb1c86909d7cac2663 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 21 Dec 2012 22:42:40 +0100 Subject: ARM: 7609/1: disable errata work-arounds which access secure registers In order to support secure and non-secure platforms in multi-platform kernels, errata work-arounds that access secure only registers need to be disabled. Make all the errata options that fit in this category depend on !CONFIG_ARCH_MULTIPLATFORM. This will effectively remove the errata options as platforms are converted over to multi-platform. Signed-off-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 350f6a74992b..26a62054f0c3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -245,7 +245,8 @@ __v7_setup: ldr r10, =0x00000c08 @ Cortex-A8 primary part number teq r0, r10 bne 2f -#ifdef CONFIG_ARM_ERRATA_430973 +#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) + teq r5, #0x00100000 @ only present in r1p* mrceq p15, 0, r10, c1, c0, 1 @ read aux control register orreq r10, r10, #(1 << 6) @ set IBE to 1 -- cgit v1.2.1 From d106de38ca927f2a53cd56ef94c506e8f6bd37e1 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 5 Jan 2013 13:57:38 +0100 Subject: ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b If CONFIG_ARCH_MULTIPLATFORM & CONFIG_ARCH_MVEBU are both enabled, __v7_pj4b_setup is added between __v7_ca9mp_setup and __v7_setup. But there's no jump instruction added. If the chip is Cortex A5/A9, it goes through __v7_pj4b_setup also. It results in system hang. Signed-off-by: Haojian Zhuang Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 26a62054f0c3..3a3c015f8d5c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -169,6 +169,7 @@ __v7_ca15mp_setup: orreq r0, r0, r10 @ Enable CPU-specific SMP bits mcreq p15, 0, r0, c1, c0, 1 #endif + b __v7_setup __v7_pj4b_setup: #ifdef CONFIG_CPU_PJ4B -- cgit v1.2.1 From 8b827c60a1d984ef8c3ed175c99a33dd451348ff Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 7 Jan 2013 11:27:14 +0100 Subject: ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable This patch fixes a bug for Aurora L2 cache controller when the write-through mode is enable. For the clean operation even if we don't have to flush the lines we still need to invalidate them. Signed-off-by: Gregory CLEMENT Tested-by: Thomas Petazzoni Acked-by: Jason Cooper Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 05d577613b13..55ca637a4930 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -506,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end) static void aurora_flush_range(unsigned long start, unsigned long end) { - if (!l2_wt_override) { - start &= ~(CACHE_LINE_SIZE - 1); - end = ALIGN(end, CACHE_LINE_SIZE); - while (start != end) { - unsigned long range_end = calc_range_end(start, end); + start &= ~(CACHE_LINE_SIZE - 1); + end = ALIGN(end, CACHE_LINE_SIZE); + while (start != end) { + unsigned long range_end = calc_range_end(start, end); + /* + * If L2 is forced to WT, the L2 will always be clean and we + * just need to invalidate. + */ + if (l2_wt_override) aurora_pa_range(start, range_end - CACHE_LINE_SIZE, - AURORA_FLUSH_RANGE_REG); - start = range_end; - } + AURORA_INVAL_RANGE_REG); + else + aurora_pa_range(start, range_end - CACHE_LINE_SIZE, + AURORA_FLUSH_RANGE_REG); + start = range_end; } } -- cgit v1.2.1 From 8a3a180d21793f2e4386b3cb61c48322564fc80a Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 7 Jan 2013 11:28:42 +0100 Subject: ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel The use of writel instead of writel_relaxed lead to deadlock in some situation (SMP on Armada 370 for instance). The use of writel_relaxed as it was done in the rest of this driver fixes this bug. Signed-off-by: Gregory CLEMENT Tested-by: Thomas Petazzoni Acked-by: Jason Cooper Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 55ca637a4930..c2f37390308a 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -460,8 +460,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end, unsigned long flags; raw_spin_lock_irqsave(&l2x0_lock, flags); - writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); - writel(end, l2x0_base + offset); + writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); + writel_relaxed(end, l2x0_base + offset); raw_spin_unlock_irqrestore(&l2x0_lock, flags); cache_sync(); @@ -675,8 +675,9 @@ static void pl310_resume(void) static void aurora_resume(void) { if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { - writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL); - writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); + writel_relaxed(l2x0_saved_regs.aux_ctrl, + l2x0_base + L2X0_AUX_CTRL); + writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); } } -- cgit v1.2.1