From 6fd02e9300bb4749750874b7c1735fd0ffc07ba9 Mon Sep 17 00:00:00 2001
From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sat, 26 May 2018 15:47:27 -0500
Subject: Add CPU SEEPROMs to Talos device tree Enable I2C bus 0 (CPU 0
 SEEPROMs) in Talos device tree

---
 arch/arm/boot/dts/aspeed-bmc-opp-talos.dts | 54 ++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

(limited to 'arch/arm/boot/dts')

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-talos.dts b/arch/arm/boot/dts/aspeed-bmc-opp-talos.dts
index 8ccb95607601..cd78c38e2be1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-talos.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-talos.dts
@@ -154,13 +154,63 @@
 };
 
 &i2c0 {
-	status = "disabled";
+	/* CPU0 */
+	status = "okay";
+
+	/* SEEPROM bank 0 */
+	eeprom@54 {
+		compatible = "atmel,24c256";
+		reg = <0x54>;
+		pagesize = <64>;
+	};
+	/* SEEPROM bank 1 */
+	eeprom@55 {
+		compatible = "atmel,24c256";
+		reg = <0x55>;
+		pagesize = <64>;
+	};
+	/* SEEPROM bank 2 */
+	eeprom@56 {
+		compatible = "atmel,24c256";
+		reg = <0x56>;
+		pagesize = <64>;
+	};
+	/* SEEPROM bank 3 */
+	eeprom@57 {
+		compatible = "atmel,24c256";
+		reg = <0x57>;
+		pagesize = <64>;
+	};
 };
 
 &i2c1 {
+	/* CPU1 */
 	status = "okay";
 
-	/* CPU1 */
+	/* SEEPROM bank 0 */
+	eeprom@54 {
+		compatible = "atmel,24c256";
+		reg = <0x54>;
+		pagesize = <64>;
+	};
+	/* SEEPROM bank 1 */
+	eeprom@55 {
+		compatible = "atmel,24c256";
+		reg = <0x55>;
+		pagesize = <64>;
+	};
+	/* SEEPROM bank 2 */
+	eeprom@56 {
+		compatible = "atmel,24c256";
+		reg = <0x56>;
+		pagesize = <64>;
+	};
+	/* SEEPROM bank 3 */
+	eeprom@57 {
+		compatible = "atmel,24c256";
+		reg = <0x57>;
+		pagesize = <64>;
+	};
 };
 
 &i2c2 {
-- 
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