From fe6c1b8611aa3a79a937a5e3b85a16576b6ad159 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Tue, 8 Jul 2014 18:43:47 +0530 Subject: ARCv2: mm: THP support MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP support. Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a new bit "SZ" in TLB page desciptor to distinguish between them. Super Page size is configurable in hardware (4K to 16M), but fixed once RTL builds. The exact THP size a Linx configuration will support is a function of: - MMU page size (typical 8K, RTL fixed) - software page walker address split between PGD:PTE:PFN (typical 11:8:13, but can be changed with 1 line) So for above default, THP size supported is 8K * 256 = 2M Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime reduces to 1 level (as PTE is folded into PGD and canonically referred to as PMD). Thus thp PMD accessors are implemented in terms of PTE (just like sparc) Signed-off-by: Vineet Gupta --- arch/arc/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arc/Kconfig') diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 78c0621d5819..5912006391ed 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -76,6 +76,10 @@ config STACKTRACE_SUPPORT config HAVE_LATENCYTOP_SUPPORT def_bool y +config HAVE_ARCH_TRANSPARENT_HUGEPAGE + def_bool y + depends on ARC_MMU_V4 + source "init/Kconfig" source "kernel/Kconfig.freezer" -- cgit v1.2.1