From 7300893c7ce63918c72b2e9121d183dac5465bfa Mon Sep 17 00:00:00 2001 From: Maxim Sloyko Date: Fri, 12 Apr 2019 07:42:06 -0700 Subject: ARM: dts: aspeed: zaius: add Infineon and Intersil regulators Add the nodes for the ir38064 and isl68137 devices on the Zaius board. OpenBMC-Staging-Count: 1 Signed-off-by: Maxim Sloyko Signed-off-by: Robert Lippert Signed-off-by: Patrick Venture Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 65 +++++++++++++++++++++++++++--- 1 file changed, 60 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 0c0ea41cbe27..53751adebf17 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -301,6 +301,32 @@ reg = <0x54>; }; }; + + }; + + vrm@64 { + compatible = "intersil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "intersil,isl68137"; + reg = <0x40>; + }; + + vrm@60 { + compatible = "intersil,isl68137"; + reg = <0x60>; + }; + + vrm@43 { + compatible = "infineon,ir38064"; + reg = <0x43>; + }; + + vrm@41 { + compatible = "intersil,isl68137"; + reg = <0x41>; }; /* Master selector PCA9541A @70h (other master: CPU0) @@ -316,18 +342,47 @@ /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ /* CPU0 VR ISL68137 0.8V PMBUS @60h */ - /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */ + /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ + /* Master selector PCA9541A @70h (other master: CPU0) + * LM5066I PMBUS @10h + */ + /* 12V SMPS Q54SH12050NNDH @61h */ }; &i2c8 { status = "okay"; - /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */ - /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */ - /* CPU1 VR ISL68137 0.8V PMBUS @61h */ + vrm@64 { + compatible = "intersil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "intersil,isl68137"; + reg = <0x40>; + }; + + vrm@41 { + compatible = "intersil,isl68137"; + reg = <0x41>; + }; + + vrm@42 { + compatible = "infineon,ir38064"; + reg = <0x42>; + }; + + vrm@60 { + compatible = "intersil,isl68137"; + reg = <0x60>; + }; + + /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */ + /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */ + /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */ /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ - /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */ + /* CPU1 VR ISL68137 0.8V PMBUS @60h */ }; -- cgit v1.2.1