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* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2018-10-291-129/+384
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "The most noteworthy SoC driver changes this time include: - The TEE subsystem gains an in-kernel interface to access the TEE from device drivers. - The reset controller subsystem gains a driver for the Qualcomm Snapdragon 845 Power Domain Controller. - The Xilinx Zynq platform now has a firmware interface for its platform management unit. This contains a firmware "ioctl" interface that was a little controversial at first, but the version we merged solved that by not exposing arbitrary firmware calls to user space. - The Amlogic Meson platform gains a "canvas" driver that is used for video processing and shared between different high-level drivers. The rest is more of the usual, mostly related to SoC specific power management support and core drivers in drivers/soc: - Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new features related to power and reset control. - The Mediatek mt8183 and mt6765 SoC platforms gain support for their respective power management chips. - A new driver for NXP i.MX8, which need a firmware interface for power management. - The SCPI firmware interface now contains support estimating power usage of performance states - The NVIDIA Tegra "pmc" driver gains a few new features, in particular a pinctrl interface for configuring the pads. - Lots of small changes for Qualcomm, in particular the "smem" device driver. - Some cleanups for the TI OMAP series related to their sysc controller. Additional cleanups and bugfixes in SoC specific drivers include the Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (129 commits) firmware: tegra: bpmp: Implement suspend/resume support drivers: clk: Add ZynqMP clock driver dt-bindings: clock: Add bindings for ZynqMP clock driver firmware: xilinx: Add zynqmp IOCTL API for device control Documentation: xilinx: Add documentation for eemi APIs MAINTAINERS: imx: include drivers/firmware/imx path firmware: imx: add misc svc support firmware: imx: add SCU firmware driver support reset: Fix potential use-after-free in __of_reset_control_get() dt-bindings: arm: fsl: add scu binding doc soc: fsl: qbman: add interrupt coalesce changing APIs soc: fsl: bman_portals: defer probe after bman's probe soc: fsl: qbman: Use last response to determine valid bit soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan soc: fsl: qbman: replace CPU 0 with any online CPU in hotplug handlers soc: fsl: qbman: Check if CPU is offline when initializing portals reset: qcom: PDC Global (Power Domain Controller) reset controller dt-bindings: reset: Add PDC Global binding for SDM845 SoCs reset: Grammar s/more then once/more than once/ bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS ...
| * soc/tegra: pmc: Implement pad configuration via pinctrlAapo Vienamo2018-08-271-2/+185
| | | | | | | | | | | | | | | | | | Register a pinctrl device and implement get and set functions for PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * soc/tegra: pmc: Remove public pad voltage APIsAapo Vienamo2018-08-271-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make tegra_io_pad_set_voltage() and tegra_io_pad_get_voltage() static and remove the prototypes from pmc.h. Remove enum tegra_io_pad_voltage and use the defines from <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> instead. These functions aren't used outside of the pmc driver and new use cases should use the pinctrl interface instead. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * soc/tegra: pmc: Use X macro to generate IO pad tablesAapo Vienamo2018-08-271-106/+127
| | | | | | | | | | | | | | | | | | Refactor the IO pad tables into macro tables so that they can be reused to generate pinctrl pin descriptors. Also add a name field which is needed by pinctrl. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * soc/tegra: pmc: Implement tegra_io_pad_is_powered()Aapo Vienamo2018-08-271-0/+15
| | | | | | | | | | | | | | | | | | Implement a function to query whether a pad is in deep power down mode. This is needed by the pinctrl callbacks. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * soc/tegra: pmc: Factor out DPD register bit calculationAapo Vienamo2018-08-271-3/+17
| | | | | | | | | | | | | | | | | | | | Factor out the the code to calculate the correct DPD register and bit number for a given pad. This logic will be needed to query the status register. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * soc/tegra: pmc: Fix pad voltage configuration for Tegra186Aapo Vienamo2018-08-271-16/+39
| | | | | | | | | | | | | | | | | | | | | | Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * soc/tegra: pmc: Fix child-node lookupJohan Hovold2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix child-node lookup during probe, which ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. To make things worse, the parent pmc node could end up being prematurely freed as of_find_node_by_name() drops a reference to its first argument. Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC") Cc: stable <stable@vger.kernel.org> # 4.0 Cc: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | soc: Convert to using %pOFn instead of device_node.nameRob Herring2018-10-041-6/+6
|/ | | | | | | | | | | | | | | | | | In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Li Yang <leoyang.li@nxp.com> Cc: David Brown <david.brown@linaro.org> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-soc@vger.kernel.org Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Qiang Zhao <qiang.zhao@nxp.com> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2018-06-091-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time we have a good set of changes to the core framework that do some general cleanups, but nothing too major. The majority of the diff goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for Actions Semi so it takes up some lines to add all the different types, and the Qualcomm diff is there because we add support for two SoCs and it's quite a bit of data. Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And then the long tail of driver updates for various fixes and stuff follows after that. Core: - debugfs cleanups removing error checking and an unused provider API - Removal of a clk init typedef that isn't used - Usage of match_string() to simplify parent string name matching - OF clk helpers moved to their own file (linux/of_clk.h) - Make clk warnings more readable across kernel versions New Drivers: - Qualcomm SDM845 GCC and Video clk controllers - Qualcomm MSM8998 GCC - Actions Semi S900 SoC support - Nuvoton npcm750 microcontroller clks - Amlogic axg AO clock controller Removed Drivers: - Deprecated Rockchip clk-gate driver Updates: - debugfs functions stopped checking return values - Support for the MSIOF module clocks on Rensas R-Car M3-N - Support for the new Rensas RZ/G1C and R-Car E3 SoCs - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs - Berlin and Amlogic SPDX tagging - Usage of of_clk_get_parent_count() in more places - Proper implementation of the CDEV1/2 clocks on Tegra20 - Allwinner H6 PRCM clock support and R40 EMAC support - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet - Round closest support for meson's mpll driver - Support for meson8b nand clocks and gxbb video decoder clocks - Mediatek mali clks - STM32MP1 fixes - Uniphier LD11/LD20 stream demux system clock" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) clk: qcom: Export clk_fabia_pll_configure() clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc clk-si544: Properly round requested frequency to nearest match clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted clk: use match_string() helper clk: bcm2835: use match_string() helper clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions clk: imx6: add EPIT clock support clk: mvebu: use correct bit for 98DX3236 NAND ...
| * soc/tegra: pmc: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2018-05-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | As of_clk_get_parent_count() returns zero on failure, while of_count_phandle_with_args() might return a negative error code, this also fixes the issue of possibly using a very big number in the allocation below. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | soc/tegra: pmc: Don't allocate struct tegra_powergate on stackViresh Kumar2018-05-081-7/+13
|/ | | | | | | | | | | | | With a later commit an instance of the struct device will be added to struct genpd and with that the size of the struct tegra_powergate will be over 1024 bytes. That generates following warning: drivers/soc/tegra/pmc.c:579:1: warning: the frame size of 1200 bytes is larger than 1024 bytes [-Wframe-larger-than=] Avoid such warnings by allocating the structure dynamically. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Use the new reset APIs to manage reset controllersVivek Gautam2018-03-191-74/+18
| | | | | | | | | | | | | Make use of of_reset_control_array_get_exclusive() to manage an array of reset controllers available with the device. Cc: Jon Hunter <jonathanh@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> [p.zabel@pengutronix.de: switch to hidden reset control array] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Pass PMC to tegra_powergate_power_up()Thierry Reding2018-03-081-0/+1
| | | | | | | | | | | | | tegra_powergate_sequence_power_up() makes up a struct tegra_powergate from scratch in order to reuse the same code as used by the generic PM domain implementation. However, subsequent patches will need to access the struct tegra_pmc * embedded in the powergate structure, so we need to make sure we always pass it in. Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: MBIST work around for Tegra210Peter De Schrijver2018-03-081-0/+12
| | | | | | | | | | | | | Apply the memory built-in self test work around when ungating certain Tegra210 power domains. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Add Tegra194 compatibility stringMikko Perttunen2018-03-081-0/+1
| | | | | | | | | The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Consolidate Tegra186 supportThierry Reding2017-12-131-1/+130
| | | | | | | | Move Tegra186 support to the consolidated PMC driver to reduce some of the duplication and also gain I/O pad functionality on the new SoC as a side-effect. Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Parameterize driverThierry Reding2017-12-131-54/+121
| | | | | | | | | | Parameterize some aspects of the driver in preparation for Tegra186 PMC support. Initially the Tegra186 driver had been split off into an extra driver, but it turns out the backwards-compatibility break isn't as bad as originally assumed, so with a little parameterization the same code can be used to keep supporting all SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: Fix bad of_node_put() in powergate initTuomas Tynkkynen2017-07-311-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The for_each_child_of_node macro itself maintains the correct reference count of the nodes so the explicit of_node_put() call causes a warning: [ 0.098960] OF: ERROR: Bad of_node_put() on /pmc@7000e400/powergates/xusba [ 0.098981] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.3 #1-NixOS [ 0.098996] Hardware name: NVIDIA Jetson TX1 Developer Kit (DT) [ 0.099011] Call trace: [ 0.099034] [<ffff00000808a048>] dump_backtrace+0x0/0x2a0 [ 0.099051] [<ffff00000808a30c>] show_stack+0x24/0x30 [ 0.099069] [<ffff0000084a6494>] dump_stack+0x9c/0xc0 [ 0.099090] [<ffff000008992214>] of_node_release+0xa4/0xa8 [ 0.099107] [<ffff0000084a9270>] kobject_put+0x90/0x1f8 [ 0.099124] [<ffff0000089914ac>] of_node_put+0x24/0x30 [ 0.099140] [<ffff00000898cec4>] __of_get_next_child+0x4c/0x70 [ 0.099155] [<ffff00000898cf28>] of_get_next_child+0x40/0x68 [ 0.099173] [<ffff0000090a099c>] tegra_pmc_early_init+0x4e8/0x5ac [ 0.099189] [<ffff00000808399c>] do_one_initcall+0x5c/0x168 [ 0.099206] [<ffff000009050c98>] kernel_init_freeable+0xd4/0x240 [ 0.099224] [<ffff000008b2d658>] kernel_init+0x18/0x108 [ 0.099238] [<ffff0000080836c0>] ret_from_fork+0x10/0x50 (It's not very apparent from the OF documentation that of_node_put() is not needed; the macro itself has no docstring and of_get_next_child() used in the implementation begins with "Returns a node pointer with refcount incremented" but then only at the very end of the docstring the crucial part "Decrements the refcount of prev" is mentioned.) Fixes: a38045121bf42 ("soc/tegra: pmc: Add generic PM domain support") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Use consistent naming for PM domainsThierry Reding2016-11-151-4/+4
| | | | | | | | | The various error messages refer to the PM domains as "power domain", "genpd" and "PM domain". That's confusing, so convert all error messages to use the most prominent: "PM domain". Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Remove genpd when adding provider failsJon Hunter2016-11-151-8/+15
| | | | | | | | | | | | | | | Commit 3fe577107ccf ("PM / Domains: Add support for removing PM domains") add support for removing PM domains. Update the Tegra PMC driver to remove PM domains if we fail to add a provider for the PM domain. Please note that the code under 'power_on_cleanup' label does not really belong in the clean-up error path for tegra_powergate_add(). To keep the error path simple, remove this label and move the associated code to where it needs to be invoked. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Check return code for pm_genpd_init()Jon Hunter2016-11-151-1/+6
| | | | | | | | | | | Commit 7eb231c337e0 ("PM / Domains: Convert pm_genpd_init() to return an error code") updated pm_genpd_init() to return an error code. Update the Tegra PMC driver to check the return value from pm_genpd_init() and handle any errors returned. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: use pr_err() instead of dev_err()] Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Clean-up I/O rail error messagesThierry Reding2016-11-151-23/+20
| | | | | | | | | | Use pr_err() instead of dev_err() when the pmc->dev field has not been initialized yet and add a few missing error messages as well as remove duplicate ones. Based on work by Jon Hunter <jonathanh@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Simplify IO rail bit handlingJon Hunter2016-11-151-10/+10
| | | | | | | | | | | | | | The function tegra_io_rail_prepare() converts the IO rail ID into a bit position that is used to check the status and control the IO rail in the PMC registers. However, rather than converting to a bit position it is more useful to convert to a bit-mask because this is what is actually used. By doing so the BIT() marco only needs to be used once and we can use the IO_DPD_REQ_CODE_MASK when checking for erroneous rail IDs. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: rebase and rename bit -> mask] Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Guard against uninitialised PMC clockJon Hunter2016-11-151-0/+2
| | | | | | | | | | | | | | It is possible for the public functions, tegra_io_rail_power_on/off() to be called before the PMC device has been probed. If this happens then the pmc->clk member will not be initialised and the call to clk_get_rate() in tegra_io_rail_prepare() will return zero and lead to a divide-by-zero exception. The function clk_get_rate() will return zero if a NULl clk pointer is passed. Therefore, rather that checking if pmc->clk is initialised, fix this by checking the return value for clk_get_rate() to make sure it is not zero. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Add I/O pad voltage supportLaxman Dewangan2016-11-151-36/+237
| | | | | | | | | | | | | | | | I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad can be used to control the common voltage signal level and power state of the pins in the given pad. I/O pads can be powered down even if the system is active, which can save power from that I/O interface. For SoC generations prior to Tegra124 the I/O pad voltage is automatically detected and hence the system software doesn't need to configure it. However, starting with Tegra210 the detection logic has been removed, so explicit control of the I/O pad voltage by system software is required. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Use consistent ordering of bit definitionsThierry Reding2016-11-151-6/+6
| | | | | | | Bit definitions are sorted in decreasing order by offset. Apply the same ordering to all definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()Laxman Dewangan2016-11-151-3/+3
| | | | | | | | | | The function tegra_pmc_readl() returns the u32 type data and hence change the data type of variable where this data is stored to u32 type. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Use BIT macro for register field definitionLaxman Dewangan2016-11-151-26/+26
| | | | | | | | | Use BIT macro for register field definition and make constant as U when using in shift operator like (3 << 30) to (3U << 30) Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Fix incorrect DPD requestVince Hsu2016-08-161-20/+8
| | | | | | | | | | Reading the DPD_REQ & DPD2_REQ registers returns the previous requests. If we sets the current request bit with the returned value, then other pads will be turned on or off unexpectedly. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Enable XUSB partitions on bootJon Hunter2016-06-301-0/+12
| | | | | | | | | | | | | | The Tegra XHCI driver does not currently manage the Tegra XUSB power partitions and so it these partitions have not been enabled by the bootloader then the system will crash when probing the XHCI device. While proper support for managing the power partitions is being developed to the XHCI driver for Tegra, for now power on all the XUSB partitions for USB host and super-speed on boot if the XHCI driver is enabled. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Initialise power partitions earlyJon Hunter2016-06-301-9/+17
| | | | | | | | | | | | | | | | | | | | | If CONFIG_PM_GENERIC_DOMAINS is not enabled, then power partitions associated with a device will not be enabled automatically by the PM core when the device is in use. To avoid situations where a device in a power partition is to be used but the partition is not enabled, initialise the power partitions for Tegra early in the boot process and if CONFIG_PM_GENERIC_DOMAINS is not enabled, then power on all partitions defined in the device-tree blob. Note that if CONFIG_PM_GENERIC_DOMAINS is not enabled, after the partitions are turned on, the clocks and resets used as part of the sequence for turning on the partition are released again as they are no longer needed by the PMC driver. Another benefit of this is that this avoids any issues of sharing resets between the PMC driver and other device drivers that may wish to independently control a particular reset. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Add specific error messagesJon Hunter2016-06-301-9/+21
| | | | | | | | | | When initialising a powergate, only a single error message is shown if the initialisation fails. Add more error messages to give specific details of what failed if the initialisation failed and remove the generic failure message. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Use whitespace more consistentlyThierry Reding2016-06-301-0/+6
| | | | | | | Use blank lines after blocks and before labels for consistency with the existing code in the file. Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Don't probe PMC if early initialisation failsJon Hunter2016-06-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0259f522e04f ('soc/tegra: pmc: Restore base address on probe failure') fixes an issue where the PMC base address pointer is not restored on probe failure. However, this fix creates another problem where if early initialisation of the PMC driver fails and an initial mapping for the PMC address space is not created, then when the PMC device is probed, the PMC base address pointer will not be valid and this will cause a crash when tegra_pmc_init() is called and attempts to access a register. Although the PMC address space is mapped a 2nd time during the probe and so this could be fixed by populating the base address pointer earlier during the probe, this adds more complexity to the code. Moreover, the PMC probe also assumes the the soc data pointer is also initialised when the device is probed and if not will also lead to a crash when calling tegra_pmc_init_tsense_reset(). Given that if the early initialisation does fail then something bad has happen, it seems acceptable to allow the PMC device probe to fail as well. Therefore, if the PMC base address pointer or soc data pointer are not valid when probing the PMC device, WARN and return an error. Fixes: 0259f522e04f ('soc/tegra: pmc: Restore base address on probe failure') Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Add missing of_node_put()Jon Hunter2016-06-301-0/+4
| | | | | | | | | Add missing of_node_put() in PMC early initialisation function to avoid leaking the device nodes. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: squash in a couple more of_node_put() calls] Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Ensure mutex is always initialisedJon Hunter2016-06-301-2/+2
| | | | | | | | | | | The mutex used by the PMC driver may not be initialised if early initialisation of the driver fails. If this does happen, then it could be possible for callers of the public PMC functions to still attempt to acquire the mutex. Fix this by initialising the mutex as soon as possible to ensure it will always be initialised. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Don't populate SoC data until register space is mappedJon Hunter2016-06-301-2/+2
| | | | | | | | | | | | | | | | | The public functions exported by the PMC driver use the presence of the SoC data pointer to determine if the PMC device is configured and the registers can be accessed. However, the SoC data is populated before the PMC register space is mapped and this opens a window where the SoC data pointer is valid but the register space has not yet been mapped which could lead to a crash. Furthermore, if the mapping of the PMC register space fails, then the SoC data pointer is not cleared and so would expose a larger window where a crash could occur. Fix this by initialising the SoC data pointer after the PMC register space has been mapped. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Fix early initialisation of PMCJon Hunter2016-06-301-16/+18
| | | | | | | | | | | | | | | | | During early initialisation, the available power partitions for a given device is configured as well as the polarity of the PMC interrupt. Both of which should only be configured if there is a valid device node for the PMC device. This is because the soc data used for configuring the power partitions is only available if a device node for the PMC is found and the code to configure the interrupt polarity uses the device node pointer directly. Some early device-tree images may not have this device node and so fix this by ensuring the device node pointer is valid when configuring these items. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Ensure powergate is available when powering onJon Hunter2016-06-301-0/+3
| | | | | | | | | | The function tegra_power_sequence_power_up() is a public function used to power on a partition. When this function is called, we do not check to see if the partition being powered up is valid/available. Fix this by checking to see that the partition is valid/available. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Initialise resets associated with a power partitionJon Hunter2016-06-301-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When registering the Tegra power partitions with the generic PM domain framework, the current state of the each partition is checked and used as the default state for the partition. However, the state of each reset associated with the partition is not initialised and so it is possible that the state of the resets are not in the expected state. For example, if a partition is on, then the resets should be de-asserted and if the partition is off, the resets should be asserted. There have been cases where the bootloader has powered on a partition and only de-asserted some of the resets to some of the devices in the partition. This can cause accesses to these devices to hang the system when the kernel boots and attempts to probe these devices. Ideally, the driver for the device should ensure the reset has been de-asserted when probing, but the resets cannot be shared between the PMC driver (that needs to de-assert/assert the reset when turning the partition on or off) and another driver because we cannot ensure the reset is in the correct state. To ensure the resets are in the correct state, when using the generic PM domain framework, put each reset associated with the partition in the correct state (based upon the partition's current state) when obtaining the resets for a partition. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Use register definitions instead of magic valuesThierry Reding2016-06-101-3/+13
| | | | | | | | | | Use register definitions for the main SoC reset operation instead of hard-coding magic values. Note that the PMC_RST_STATUS register isn't actually accessed, but since it is mentioned in a comment the definitions are added for completeness. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Add generic PM domain supportJon Hunter2016-04-291-61/+424
| | | | | | | | | | | | | | | | | | | | | | | | | Adds generic PM domain support to the PMC driver where the PM domains are populated from device-tree and the PM domain consumer devices are bound to their relevant PM domains via device-tree as well. Update the tegra_powergate_sequence_power_up() API so that internally it calls the same tegra_powergate_xxx functions that are used by the Tegra generic PM domain code for consistency. To ensure that the Tegra power domains (a.k.a. powergates) cannot be controlled via both the legacy tegra_powergate_xxx functions as well as the generic PM domain framework, add a bit map for available powergates that can be controlled via the legacy powergate functions. Move the majority of the tegra_powergate_remove_clamping() function to a sub-function, so that this can be used by both the legacy and generic power domain code. This is based upon work by Thierry Reding <treding@nvidia.com> and Vince Hsu <vinceh@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Wait for powergate state to changeJon Hunter2016-04-051-1/+8
| | | | | | | | | | | | | | | | | | | | Currently, the function tegra_powergate_set() simply sets the desired powergate state but does not wait for the state to change. In most cases we should wait for the state to change before proceeding. Currently, there is a case for Tegra114 and Tegra124 devices where we do not wait when starting the secondary CPU as this is not necessary. However, this is only done at boot time and so waiting here will only have a small impact on boot time. Therefore, update tegra_powergate_set() to wait when setting the powergate. By adding this feature, we can also eliminate the polling loop from tegra30_boot_secondary(). A function has been added for checking the status of the powergate and so update the tegra_powergate_is_powered() to use this macro as well. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Ensure GPU partition can be toggled on/off by PMCJon Hunter2016-04-051-1/+7
| | | | | | | | | | | | | | | | | | | | | | | For Tegra124 and Tegra210, the GPU partition cannot be toggled on and off via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the partition is simply powered up and down via an external regulator. For these devices, there is a separate register for controlling the signal clamping of the partition and this is described in the PMC SoC data by the "has_gpu_clamp" variable. Use this variable to determine if the GPU partition can be controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0 register and ensure that no one can incorrectly try to toggle the GPU partition via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. Furthermore, we cannot use the APBDEV_PMC_PWRGATE_STATUS_0 register to determine if the GPU partition is powered for Tegra124 and Tegra210. However, if the GPU partition is powered, then the signal clamp for the GPU partition should be removed and so use bit 0 of the APBDEV_PMC_GPU_RG_CNTRL_0 register to determine if the clamp has been removed (bit[0] = 0) and the GPU partition is powered. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Remove additional check for a valid partitionJon Hunter2016-04-051-2/+4
| | | | | | | | | | | The function tegra_powergate_is_powered() verifies that the partition being queried is valid and so there is no need to check this before calling tegra_powergate_is_powered() in powergate_show(). So remove this extra check. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Fix verification of valid partitionsJon Hunter2016-04-051-4/+9
| | | | | | | | | | | | | | | | The Tegra power partitions are referenced by numerical IDs which are the same values programmed into the PMC registers for controlling the partition. For a given device, the valid partition IDs may not be contiguous and so simply checking that an ID is not greater than the maximum ID supported may not mean it is valid. Fix this by checking if the powergate is defined in the list of powergates for the Tegra SoC. Add a helper function for checking valid powergates and use where we need to verify if the powergate ID is valid or not. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Fix testing of powergate stateJon Hunter2016-04-051-8/+9
| | | | | | | | | | | | | | | | | | | | In tegra_powergate_set() the state of the powergates is read and OR'ed with the bit for the powergate of interest. This unsigned 32-bit value is then compared with a boolean value to test if the powergate is already in the desired state. When turning on a powergate, apart from the powergate that is represented by bit 0, this test will always return false and so we may attempt to turn on the powergate when it is already on. After OR'ing the bit for the powergate, check if the result is not equal to zero before comparing with the boolean value. Add a helper function to return the current state of a powergate and use this in both tegra_powergate_set() and tegra_powergate_is_powered() where we check the powergate status. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Change powergate and rail IDs to be an unsigned typeJon Hunter2016-04-051-18/+18
| | | | | | | | | | The Tegra powergate and rail IDs are always positive values and so change the type to be unsigned and remove the tests to see if the ID is less than zero. Update the Tegra DC powergate type to be an unsigned as well. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* soc/tegra: pmc: Protect public functions from potential race conditionsJon Hunter2016-04-051-14/+33
| | | | | | | | | | | | | | | | | | | | | | | | | The PMC base address pointer is initialised during early boot so that early platform code may used the PMC public functions. During the probe of the PMC driver the base address pointer is mapped again and the initial mapping is freed. This exposes a window where a device accessing the PMC registers via one of the public functions, could race with the updating of the pointer and lead to a invalid access. Furthermore, the only protection between multiple devices attempting to access the PMC registers is when setting the powergate state to on or off. None of the other public functions that access the PMC registers are protected. Use the existing mutex to protect paths that may race with regard to accessing the PMC registers. Note that functions tegra_io_rail_prepare()/poll() either return a negative value on failure or zero on success. Therefore, it is not necessary to check if the return value is less than zero and so only test that the return value is not zero to test for failure. This simplifies the error handling with the mutex locking in place. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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