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path: root/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
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* pinctrl: sh-pfc: r8a7794: Add can_clk functionFabrizio Castro2017-12-051-0/+20
| | | | | | | | | | | This patch adds can_clk function to r8a7745/r8a7794 which is cleaner, and allows for independent configuration. We keep the can_clk* pins definitions from within can0_groups and can1_groups for uniformity and backwards compatibility. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7745: Add CAN[01] supportFabrizio Castro2017-11-281-0/+146
| | | | | | | | | This patch adds PFC CAN0 and CAN1 pin groups and functions, enabling CAN bus on the RZ/G1E. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7745: Implement voltage switching for SDHIBiju Das2017-10-161-0/+1
| | | | | | | Voltage switching is the same as on the r8a7794. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add R8A7745 supportSergei Shtylyov2017-05-161-2/+25
| | | | | | | | | | | Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794), however it doesn't have several automotive specific peripherals. Annotate all the items that only exist on the R-Car SoCs... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> [geert: Drop annotations, as they are implied by pin groups/functions] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Remove reserved bitsSergei Shtylyov2017-05-161-588/+529
| | | | | | | | | | | | | | | The R8A7794 PFC driver was apparently based on the preliminary revisions of the user's manual which had some signals and MOD_SEL register fields described which the recent manual changed to reserved. Of course, these signals haven't ever been really used, which makes removing them painless. While at it, make the large *enum* look better by starting a new line each time a new row in the IPSR and MOD_SEL register field tables is started. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Remove AVB_AVTP_* groupsSergei Shtylyov2017-05-161-32/+0
| | | | | | | | | | | The ATA_AVTP_* signals are documented as reserved in the recent R-Car E2 user's manual (the only remaining mention is in the table 5.2 and I believe it's a simple overlook). Remove the AVB_AVTP_* pinmux groups -- we will remove the signals themselves in the next patch, along with the other now reserved bits... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Rename some I2C signalsSergei Shtylyov2017-05-161-69/+69
| | | | | | | | | | The R8A7794 PFC driver was apparently based on the preliminary revisions of the user's manual which called I2C5 device IIC0 and IIC0 device IIC1. Luckily, these signals haven't been used for any functions/groups so far, so the renaming should be painless.. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Swap ATA signalsSergei Shtylyov2017-04-051-8/+8
| | | | | | | | | All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this. Fixes: 43c4436e2f18 ("pinctrl: sh-pfc: add R8A7794 PFC support") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHISimon Horman2016-09-141-1/+27
| | | | | | | | | | | | All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add DU pin groupsKoji Matsuoka2016-04-151-0/+217
| | | | | | | | | | | | | | | | | | r8a7794 PFC DU support from the R-Car Gen2 v1.9.4 BSP [Magnus: added the description, added missing dot clock output signals, separated CDE and DISP signals, broke out the ODDF signal from the sync group.] [Sergei: resolved rejects, folded in Magnus' patches, killed empty lines, reordered pin/mux arrays and pin groups, fixed up some comments to the pin arrays, removed the "du" function splitting its groups between the "du0" and "du1" functions.] Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Fix GP2[29] muxingAndrey Gusakov2016-02-261-0/+1
| | | | | | | | | | | GP2[29] muxing is controlled by 2-bit IP6[3:2] field, yet only 3 values are listed instead of 4... [Sergei: fixed up the formatting, renamed, added the changelog.] Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add EtherAVB pin groupsSergei Shtylyov2016-02-181-0/+123
| | | | | | | | | Add the EtherAVB pin groups to the R8A7794 PFC driver. Based on the patches by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add audio clock pin groupsRyo Kataoka2016-02-181-0/+122
| | | | | | | | | | | | | Add the audio clock pin groups to the R8A7794 PFC driver. [Sergei: fixed pin group names to reflect the reality, fixed pin names in the comments to *_pins[], lowercased the separator comment, resolved rejects, added the changelog, renamed the patch.] Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Add SSI pin groupsRyo Kataoka2016-02-181-2/+313
| | | | | | | | | | | | | | Add the SSI pin groups to the R8A7794 PFC driver. [Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin groups into data/control ones, moved SSI7 data B group to its proper place, fixed pin names in the comments to *_pins[], extended Cogent Embedded's copyright, added the changelog, renamed the patch.] Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: Rename PINMUX_IPSR_DATA() to PINMUX_IPSR_GPSR()Geert Uytterhoeven2016-02-081-422/+422
| | | | | | | | | | This macro describes a pinmux configuration that needs configuration in both a Peripheral Function Select Register (IPSR) and in a GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the macro name for clarity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* pinctrl: sh-pfc: r8a7794: Add SCIF_CLK supportGeert Uytterhoeven2015-12-161-0/+23
| | | | | | | | | | Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Share/reuse same PORT_GP_x() macrosKuninori Morimoto2015-11-301-19/+0
| | | | | | | | | Many SoC needs each PORT_GP_x() macros, but we can share/reuse same one. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Use PINMUX_SINGLE() instead of raw PINMUX_DATA()Geert Uytterhoeven2015-11-301-22/+22
| | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* pinctrl: sh-pfc: Stop including <linux/platform_data/gpio-rcar.h>Geert Uytterhoeven2015-10-201-1/+0
| | | | | | | | | | This header file will be removed soon. Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl drivers only, to sh_pfc.h, and drop the #include. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: Rename .gpio_data[] to .pinmux_data[]Geert Uytterhoeven2015-10-201-2/+2
| | | | | | | | | | | The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but also various other pinmux-related data (functions and marks). Every single driver already calls its local array pinmux_data[]. Hence rename the sh_pfc_soc_info member to "pinmux_data". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* pinctrl: sh-pfc: r8a7794: Add VIN pin groupsKoji Matsuoka2015-10-201-0/+184
| | | | | | | | | | | | | Add VIN0/1 pin groups to R8A7794 PFC driver. Sergei: rebased, renamed, added changelog, gathered 12 VIN1 data pins into a single pin group, added "vin1_data10" pin group, used 'union vin_data' and VIN_DATA_PIN_GROUP() macro to describe VIN1 pins, reversed the order of the VIN1 pin groups, removed unneeded empty lines, fixed VIN1 separator comment. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: use PINMUX_IPSR_MSEL()Kuninori Morimoto2015-10-021-414/+414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* pinctrl: sh-pfc: r8a7794: Remove bogus SCIF0 SCK pin dataGeert Uytterhoeven2015-10-021-18/+0
| | | | | | | | | | SCIF0 on R-Car E2 does not have an SCK pin. "SCIF_CLK" is the (H)SCIF baud rate generation clock pin, which is not yet supported. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7794: add USB pin groupsShinobu Uehara2015-08-261-0/+30
| | | | | | | | | | Add USB0/1 pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [Sergei: rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7794: add SDHI pin groupsShinobu Uehara2015-06-161-0/+153
| | | | | | | | | | | Add SDHI0/1/2 pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [Sergei: renamed SD data pins to match the driver, rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7794: add MMCIF pin groupsShinobu Uehara2015-06-161-0/+46
| | | | | | | | | | Add MMCIF pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [Sergei: rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: add R8A7794 PFC supportHisashi Nakamura2015-06-161-0/+4008
Add PFC support for the R8A7794 SoC including pin groups for some on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF... Sergei: squashed together several patches, fixed the MLB_CLK typo, added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin group names, removed stray new line and fixed typos in the comments in the pinmux_config_regs[] initializer, removed the platform device ID, took into account limited number of signals in the GPIO1/5/6 controllers, added reasonable and removed unreasonable copyrights, modified the bindings document, renamed, added changelog. Changes in version 5: - resolved rejects, refreshed the patch; - added Laurent Pinchart's ACK. Changes in version 4: - reused the PORT_GP_26() macro to #define PORT_GP_28(). Changes in version 3: - removed the platform device ID; - added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the CPU_ALL_PORT() macro. Changes in version 2: - rebased the patch. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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