| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | drm/nva3/clk: better pll calculation when no fractional fb div available | Ben Skeggs | 2011-05-16 | 1 | -31/+37 |
| | | | | | | | | | | | | | The core/mem/shader clocks don't support the fractional feedback divider, causing our calculated clocks to be off by quite a lot in some cases. To solve this we will switch to a search-based algorithm when fN is NULL. For my NVA8 at PL3, this actually generates identical cooefficients to the binary driver. Hopefully that's a good sign, and that does not break VPLL calculation for someone.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | ||||
| * | drm/nva3: fix overflow in fixed point math used for pll calculation | Ben Skeggs | 2010-11-18 | 1 | -6/+10 |
| | | | | | | | And a slight tweak which gets us closer to VBIOS-calculated numbers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | ||||
| * | drm/nv50: support fractional feedback divider on newer chips | Ben Skeggs | 2010-05-19 | 1 | -0/+87 |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> | |||||
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