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* drm/msm: gpu: Use OPP tables if we canJordan Crouse2017-04-081-19/+66
| | | | | | | | | | If a OPP table is defined for the GPU device in the device tree use that in lieu of the downstream style GPU frequency table. If we do use the downstream table convert it to a OPP table so that we can take advantage of the OPP lookup facilities later. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Hard code the GPU "slow frequency"Jordan Crouse2017-04-083-8/+4
| | | | | | | | | | | | | | | | | | | | | Some A3XX and A4XX GPU targets required that the GPU clock be programmed to a non zero value when it was disabled so 27Mhz was chosen as the "invalid" frequency. Even though newer targets do not have the same clock restrictions we still write 27Mhz on clock disable and expect the clock subsystem to round down to zero. For unknown reasons even though the slow clock speed is always 27Mhz and it isn't actually a functional level the legacy device tree frequency tables always defined it and then did gymnastics to work around it. Instead of playing the same silly games just hard code the "slow" clock speed in the code as 27MHz and save ourselves a bit of infrastructure. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Add MSM_PARAM_GMEM_BASEJordan Crouse2017-04-081-0/+3
| | | | | | | | User space needs to know where the GMEM whole starts so that they can set up the addressing correctly. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Reference count address spacesJordan Crouse2017-04-081-1/+1
| | | | | | | | | | | There are reasons for a memory object to outlive the file descriptor that created it and so the address space that a buffer object is attached to must also outlive the file descriptor. Reference count the address space so that it can remain viable until all the objects have released their addresses. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Make sure to detach the MMU during GPU cleanupJordan Crouse2017-04-081-10/+19
| | | | | | | | | | | We should be detaching the MMU before destroying the address space. To do this cleanly, the detach has to happen in adreno_gpu_cleanup() because it needs access to structs in adreno_gpu.c. Plus it is better symmetry to have the attach and detach at the same code level. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Pass interrupt status to a5xx_rbbm_err_irq()Jordan Crouse2017-04-081-5/+13
| | | | | | | | | | | | | | The interrupt status was being cleared before processing the handlers. a5xx_rbbm_err_irq() was checking the interrupt status again, which would likely turn out bad because the interrupt status would be 0 (or at least different). Pass the original status to the function instead. Also, skip clearing RBBM_AHB_ERROR from the interrupt status. The interrupt will keep firing until the error source is cleared. Skip the clear to avoid a storm until the error is cleared in a5xx_rbbm_err_irq(). Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Fix wrong pointer check in a5xx_destroyJordan Crouse2017-04-081-2/+2
| | | | | | | | Instead of checking for a5xx_gpu->gpmu_iova during destroy we accidently check a5xx_gpu->gpmu_bo. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: adreno: fix build error without debugfsArnd Bergmann2017-04-081-0/+2
| | | | | | | | | | | | | | The newly added a5xx support fails to build when debugfs is diabled: drivers/gpu/drm/msm/adreno/a5xx_gpu.c:849:4: error: 'struct msm_gpu_funcs' has no member named 'show' drivers/gpu/drm/msm/adreno/a5xx_gpu.c:849:11: error: 'a5xx_show' undeclared here (not in a function); did you mean 'a5xx_irq'? This adds a missing #ifdef. Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support") Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: reset ringbuffer in hw_initRob Clark2017-04-081-10/+8
| | | | | | We need to do this also in resume path when we need to re-hw_init(). Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/gpu: use pm-runtimeRob Clark2017-04-082-13/+34
| | | | | | | We need to use pm-runtime properly when IOMMU is using device_link() to control it's own clocks. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/gpu: move suspend/resume into debugfs->showRob Clark2017-04-084-14/+0
| | | | | | | Each of the per-generation callbacks was doing this. Lets just simplify and move it into toplevel show() fxn. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: let gpu wire up it's own fault handlerRob Clark2017-02-061-0/+17
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: drop quirks bindingRob Clark2017-02-064-20/+7
| | | | | | | | | | This was never documented or used in upstream dtb. It is used by downstream bindings from android device kernels. But the quirks are a property of the gpu revision, and as such are redundant to be listed separately in dt. Instead, move the quirks to the device table. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* drm/msm: drop qcom,chipidRob Clark2017-02-061-1/+39
| | | | | | | | | | | | | | | The original way we determined the gpu version was based on downstream bindings from android kernel. A cleaner way is to get the version from the compatible string. Note that no upstream dtb uses these bindings. But the code still supports falling back to the legacy bindings (with a warning), so that we are still compatible with the gpu dt node from android device kernels. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
* drm/msm: remove qcom,gpu-pwrlevels bindingsRob Clark2017-02-061-2/+4
| | | | | | | | | | | | | | The plan is to use the OPP bindings. For now, remove the documentation for qcom,gpu-pwrlevels, and make the driver fall back to a safe low clock if the node is not present. Note that no upstream dtb use this node. For now we keep compatibility with this node to avoid breaking compatibility with downstream android dt files. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
* drm/msm: fix potential null ptr issue in non-iommu caseRob Clark2017-01-131-3/+2
| | | | | | Fixes: 9cb07b099fb ("drm/msm: support multiple address spaces") Reported-by: Riku Voipio <riku.voipio@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Ensure that the hardware write pointer is validJordan Crouse2016-12-291-1/+8
| | | | | | | | | | | | | | | | Currently the value written to CP_RB_WPTR is calculated on the fly as (rb->next - rb->start). But as the code is designed rb->next is wrapped before writing the commands so if a series of commands happened to fit perfectly in the ringbuffer, rb->next would end up being equal to rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR. The easiest way to fix this is to mask WPTR when writing it to the hardware; it makes the hardware happy and the rest of the ringbuffer math appears to work and there isn't any point in upsetting anything. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [squash in is_power_of_2() check] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: gpu: Add support for the GPMUJordan Crouse2016-11-285-3/+430
| | | | | | | | | | | | | | | | | | | | Most 5XX targets have GPMU (Graphics Power Management Unit) that handles a lot of the heavy lifting for power management including thermal and limits management and dynamic power collapse. While the GPMU itself is optional, it is usually nessesary to hit aggressive power targets. The GPMU firmware needs to be loaded into the GPMU at init time via a shared hardware block of registers. Using the GPU to write the microcode is more efficient than using the CPU so at first load create an indirect buffer that can be executed during subsequent initalization sequences. After loading the GPMU gets initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: gpu: Add A5XX target supportJordan Crouse2016-11-285-5/+933
| | | | | | | Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Disable interrupts during initJordan Crouse2016-11-282-0/+7
| | | | | | | | | Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7Jordan Crouse2016-11-281-0/+30
| | | | | | | | Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Add adreno_gpu_write64()Jordan Crouse2016-11-284-5/+34
| | | | | | | | | | | | | | | | | | | Add a new generic function to write a "64" bit value. This isn't actually a 64 bit operation, it just writes the upper and lower 32 bit of a 64 bit value to a specified LO and HI register. If a particular target doesn't support one of the registers it can mark that register as SKIP and writes/reads from that register will be quietly dropped. This can be immediately put in place for the ringbuffer base and the RPTR address. Both writes are converted to use adreno_gpu_write64() with their respective high and low registers and the high register appropriately marked as SKIP for both 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: gpu Add new gpu register read/write functionsJordan Crouse2016-11-281-10/+2
| | | | | | | | | | | | | | Add some new functions to manipulate GPU registers. gpu_read64 and gpu_write64 can read/write a 64 bit value to two 32 bit registers. For 4XX and older these are normally perfcounter registers, but future targets will use 64 bit addressing so there will be many more spots where a 64 bit read and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: gpu: Return error on hw_init failureJordan Crouse2016-11-284-25/+29
| | | | | | | | | When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: gpu: Cut down the list of "generic" registers to the ones we useJordan Crouse2016-11-283-215/+0
| | | | | | | | | | There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2016-11-286-96/+4158
| | | | | | Pull in a5xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: move scratch register dumping to per-gen codeRob Clark2016-11-283-6/+14
| | | | | | | Scratch registers move, annoyingly enough, in a5xx. Move to per-generation aNxx_recover() fxn. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: convert iova to 64bRob Clark2016-11-281-1/+1
| | | | | | | | | For a5xx the gpu is 64b so we need to change iova to 64b everywhere. On the display side, iova is still 32b so it can ignore the upper bits. (Although all the armv8 devices have an iommu that can map 64b pa to 32b iova.) Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: support multiple address spacesRob Clark2016-11-273-3/+3
| | | | | | | | We can have various combinations of 64b and 32b address space, ie. 64b CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So best to decouple the device iova's from mmap offset. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: move function declarations to header fileBaoyou Xie2016-10-242-3/+3
| | | | | | | | | | | | | | | | We get 2 warnings when building kernel with W=1: drivers/gpu/drm/msm/adreno/a3xx_gpu.c:535:17: warning: no previous prototype for 'a3xx_gpu_init' [-Wmissing-prototypes] drivers/gpu/drm/msm/adreno/a4xx_gpu.c:624:17: warning: no previous prototype for 'a4xx_gpu_init' [-Wmissing-prototypes] In fact, both functions are declared in drivers/gpu/drm/msm/adreno/adreno_device.c, but should be declared in a header file. So this patch moves both function declarations to drivers/gpu/drm/msm/adreno/adreno_gpu.h. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1477127865-9381-1-git-send-email-baoyou.xie@linaro.org
* drm/msm: deal with arbitrary # of cmd buffersRob Clark2016-07-161-9/+2
| | | | | | | | For some optimizations coming on the userspace side, splitting larger draw or gmem cmds into multiple cmdstream buffers, we need to support much more than the previous small/arbitrary limit. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: change gem->vmap() to get/putRob Clark2016-07-161-1/+5
| | | | | | | | Before we can add vmap shrinking, we really need to know which vmap'ings are currently being used. So switch to get/put interface. Stubbed put fxns for now. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: deal with exhausted vmap space betterRob Clark2016-06-041-1/+1
| | | | | | | | Some, but not all, callers of obj->vmap() would check if return IS_ERR(). So let's actually return an error if vmap() fails. And fixup the call-sites that were not handling this properly. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: drop return from gpu->submit()Rob Clark2016-05-082-4/+2
| | | | | | | | At this point, there is nothing left to fail. And submit already has a fence assigned and is added to the submit_list. Any problems from here on out are asynchronous (ie. hangcheck/recovery). Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: fix ->last_fence() after recoverRob Clark2016-05-081-2/+2
| | | | | | | | | | It is no longer true that we discard all in-flight submits on recover (these days we only discard the first one that hung). After the first re-submitted batch completes it would overwrite the fence with a correct value, but there would be a window of time which showed all re-submitted batches as already complete. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: 'struct fence' conversionRob Clark2016-05-081-2/+2
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: introduce msm_fence_contextRob Clark2016-05-081-3/+3
| | | | | | | | Better encapsulate the per-timeline stuff into fence-context. For now there is just a single fence-context, but eventually we'll also have one per-CRTC to enable fully explicit fencing. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: remove duplicate adreno_hw_init() callRob Clark2016-03-031-6/+0
| | | | | | | Not sure where it came from, but seem unintentional. And also not needed on a420, so let's just drop it. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add timestamp paramRob Clark2016-03-033-0/+28
| | | | | | | | | | | | | | We need this for GL_TIMESTAMP queries. Note: currently only supported on a4xx.. a3xx doesn't have this always-on counter. I think we could emulate it with the one CP counter that is available, but for now it is of limited usefulness on a3xx (since we can't seem to do time-elapsed queries in any sane way with the existing firmware on a3xx, and if you are trying to do profiling on a tiler you want time-elapsed). We can add that later if it becomes useful. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: print details in case of a protect fault interruptCraig Stout2016-03-031-0/+7
| | | | | Signed-off-by: Craig Stout <cstout@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: get CP_RPTR from register instead of shadow memoryCraig Stout2016-03-031-12/+22
| | | | | | | | | As described in the downstream/kgsl driver: Sometimes the RPTR shadow memory is unreliable causing timeouts in adreno_idle(). Read it directly from the register instead. Signed-off-by: Craig Stout <cstout@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: add adreno430 power controlCraig Stout2016-03-031-2/+37
| | | | | Signed-off-by: Craig Stout <cstout@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: support for adreno 430.Craig Stout2016-03-034-7/+52
| | | | | Signed-off-by: Craig Stout <cstout@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2016-03-035-145/+1704
| | | | | | Pull in additional regs needed for a430, etc. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add max-freq gpu param to uapiRob Clark2016-02-111-0/+3
| | | | | | | | | | | | We need this in userspace for interpreting some of the perf ctrs. Note possibly not quite sufficient if we had some frequency mgmt approach other than race-to-idle. Not really sure what the best thing to do if we did. Although displaying results as a percentage of max frequence seems sensible(ish) if we did. Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/msm/adreno: Remove CONFIG_OF checksArchit Taneja2015-12-141-52/+0
| | | | | | | | Remove CONFIG_OF checks in adreno_device.c. The downstream bus scaling stuff is included only when CONFIG_OF is not set. So, remove that too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-10-225-22/+51
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-08-155-45/+248
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: workaround for missing irq on a306/8x16Rob Clark2015-06-111-0/+11
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: adreno a306 supportRob Clark2015-06-113-3/+23
| | | | | | | | | As found in apq8016 (used in DragonBoard 410c) and msm8916. Note that numerically a306 is actually 307 (since a305c already claimed 306). Nice and confusing. Signed-off-by: Rob Clark <robdclark@gmail.com>
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