summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_ddi.c
Commit message (Collapse)AuthorAgeFilesLines
...
* drm/i915: Unify error handling for missing DDI buf trans tablesVille Syrjälä2017-10-191-5/+22
| | | | | | | | | | | | | Handle missing buf trans tables, or out of bounds buf trans levels the same way everywhere. These should never be hit under normal conditions, but let's play it safe for now. v2: Avoid the hdmi_level=-1 case (James) Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171018181934.4229-1-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915: Centralize the SKL DDI A/E vs. B/C/D buf trans handlingVille Syrjälä2017-10-191-26/+34
| | | | | | | | | | | | | | | | | | SKL DDI B/C/D only have 9 usable buf trans registers for DP/eDP. That matches the normal DP buf trans tables, but the low vswing eDP tables have 10 entries. Thus the eDP tables can only be used safely with DDI A and E. We try to catch cases where DDI B/C/D gets used with the wrong number of entires in some parts of the code, but not everywhere. Let's move the code to deal with that deeper into intel_ddi_get_buf_trans_edp(). And for sake of symmetry do the same in intel_ddi_get_buf_trans_dp(). That would also avoid explosions in the rather unlikely case that the DP tables would get revised to 10 entries as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-9-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915: Kill off the BXT buf_trans default_indexVille Syrjälä2017-10-191-46/+34
| | | | | | | | | | | default_index contained in the BXT buf_trans tables is actually useless. For DP we should always have a valid level selected (otherwise the link training logic would be buggy), and for HDMI we can just do what the other platforms do and pick the correct entry in intel_ddi_hdmi_level(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-8-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitlyVille Syrjälä2017-10-191-28/+25
| | | | | | | | | | | | encoder->type is unreliable for DP/HDMI, so pass it in explicity into cnl_ddi_vswing_sequence(). This matches what we do for BXT. v2: Pass intel_encoder down to cnl_ddi_vswing_program(), and clean up the argument types while at it Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-7-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915: Integrate BXT into intel_ddi_dp_voltage_max()Ville Syrjälä2017-10-191-24/+45
| | | | | | | | | | | Make BXT less special by following the CNL approach and handling it in intel_ddi_dp_voltage_max() alognside every other DDI platform. v2: Clean up the argument types to bxt_ddi_vswing_sequence() while at it Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-6-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915: Pass the level to intel_prepare_hdmi_ddi_buffers()Ville Syrjälä2017-10-191-5/+4
| | | | | | | | | The caller of intel_prepare_hdmi_ddi_buffers() alreday figured out the level, so let's just pass it in instead if figuring it out again. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-5-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915: Pass the encoder type explicitly to skl_set_iboost()Ville Syrjälä2017-10-191-35/+22
| | | | | | | | | | | | encoder->type isn't reliable for DP/HDMI encoders, so pass the type explicity to skl_set_iboost(). Also take the opportunity to streamline the code. v2: Clean up the argument types to skl_ddi_set_iboost() while at it Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-4-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915: Extract intel_ddi_get_buf_trans_hdmi()Ville Syrjälä2017-10-191-22/+28
| | | | | | | | | | Introduce intel_ddi_get_buf_trans_hdmi() and start using it where we can. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-3-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
* drm/i915: Relocate intel_ddi_get_buf_trans_*() functionsVille Syrjälä2017-10-191-60/+55
| | | | | | | | | | | | We'll want to use the intel_ddi_get_buf_trans_*() functions a bit earlier in the file, so move them up. While at it start using them in the iboost setup to get rid of the platform checks there. v2: Rebase due to BDW FDI buf trans fix Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-2-ville.syrjala@linux.intel.com Reviewed-by: James Ausmus <james.ausmus@intel.com>
* drm/i915/cnl: Fix PLL mapping.Rodrigo Vivi2017-10-161-2/+1
| | | | | | | | | | | | | | | | | | | | | On PLL Enable sequence we need to "Configure DPCLKA_CFGCR0 to turn on the clock for the DDI and map the DPLL to the DDI" So we first do the map and then we unset DDI_CLK_OFF to turn the clock on. We do this in 2 separated steps. However, on this second step where we should only unset the off bit we are also unmapping the ddi from the pll. So we end up using the pll 0 for almost everything. Consequently breaking cases with more than one display. Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping") Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Kahola, Mika <mika.kahola@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003220859.21352-2-rodrigo.vivi@intel.com
* drm/i915: Use bdw_ddi_translations_fdi for BroadwellChris Wilson2017-10-131-2/+2
| | | | | | | | | | | | | | | | | | | The compiler warns: drivers/gpu/drm/i915/intel_ddi.c:118:35: warning: ‘bdw_ddi_translations_fdi’ defined but not used Lo and behold, if we look at intel_ddi_get_buf_trans_fdi(), it uses hsw_ddi_translations_fdi[] for both Haswell and *Broadwell* Fixes: 7d1c42e679f9 ("drm/i915: Refactor code to select the DDI buf translation table") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: David Weinehall <david.weinehall@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: <stable@vger.kernel.org> # v4.12+ Link: https://patchwork.freedesktop.org/patch/msgid/20171013154735.27163-1-chris@chris-wilson.co.uk Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
* drm/i915: Split intel_enable_ddi() into DP and HDMI variantsVille Syrjälä2017-10-131-34/+46
| | | | | | | | | | | Untangle intel_enable_ddi() by splitting it into DP and HDMI specific variants. v2: Keep using intel_ddi_get_encoder_port() for now Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Plumb crtc_state etc. directly to intel_ddi_pre_enable_{dp,hdmi}()Ville Syrjälä2017-10-131-34/+20
| | | | | | | | | | | | | | | | | Rather that plumb the link parameters separately to intel_ddi_pre_enable_dp() let's just pass the entire crtc state. intel_ddi_pre_enable_hdmi() already took the crtc state, but for some reason intel_ddi_pre_enable() still wanted to extract has_infoframe from therein and pass it in separately. Let's not do that since it's pointless. v2: Rebase due to more code getting pulled into the DDI hooks Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Split intel_disable_ddi() into DP vs. HDMI variantsVille Syrjälä2017-10-131-17/+28
| | | | | | | | | Untangle intel_disable_ddi() by splitting it into DP and HDMI specific variants. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Remove useless eDP check from intel_ddi_pre_enable_dp()Ville Syrjälä2017-10-131-2/+2
| | | | | | | | | | intel_edp_panel_on() will itself do the is_edp() check, so the caller doesn't have to bother. Pre-DDI code doesn't bother, so let's follow the same approach for DDI. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-7-ville.syrjala@linux.intel.com
* drm/i915: Split intel_ddi_post_disable() into DP vs. HDMI variantsVille Syrjälä2017-10-131-39/+56
| | | | | | | | | | | To clean up the mess in intel_ddi_post_disable() split it into two clean variants for HDMI and DP. v2: Rebase due to MST DPMS changes Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-6-ville.syrjala@linux.intel.com
* drm/i915: Inline the required bits of intel_ddi_post_disable() into ↵Ville Syrjälä2017-10-131-1/+2
| | | | | | | | | | | | intel_ddi_fdi_post_disable() To untangle the mess that is intel_ddi_post_disable() move the the bits needed by FDI into intel_ddi_fdi_post_disable(). This way we can stop worrying about FDI in intel_ddi_post_disable(). Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-5-ville.syrjala@linux.intel.com
* drm/i915: Extract intel_disable_ddi_buf()Ville Syrjälä2017-10-131-17/+24
| | | | | | | | | | | | Extract the code to disable the DDI_BUF_CTL into small helper. This will allows us to detangle the encoder type mess in intel_ddi_post_disable(). v2: Keep using intel_ddi_get_encoder_port() for now Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-4-ville.syrjala@linux.intel.com
* drm/i915: Extract intel_ddi_clk_disable()Ville Syrjälä2017-10-131-8/+16
| | | | | | | | | | | | Pull the code to disable the port clock into a function. We already have the intel_ddi_clk_select() counterpart. v2: Keep using intel_ddi_get_encoder_port() for now (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010121207.570-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: avoid division by zero on cnl_calc_wrpll_linkPaulo Zanoni2017-10-091-0/+3
| | | | | | | | | | | | | | | If for some unexpected reason the registers all read zero it's better to WARN and return instead of dividing by zero and completely freezing the machine. I don't expect this to happen in the wild with the current code, but I accidentally triggered the division by zero while doing some debugging in an unusual environment. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171005213842.11423-2-paulo.r.zanoni@intel.com
* drm/i915: push DDI and DSI underrun reporting on enable to encoderJani Nikula2017-10-061-0/+8
| | | | | | | | | | Simplify CRTC enable. v2: Don't forget DSI (Daniel) Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1ad8f3ccaed99a5f03e3d53345221a25ad0be50f.1507200657.git.jani.nikula@intel.com
* drm/i915: avoid potential uninitialized variable useArnd Bergmann2017-10-051-3/+9
| | | | | | | | | | | | | | | | | | | | One of the recent changes introduced a warning about undefined behavior in the sanity checking: drivers/gpu/drm/i915/intel_ddi.c: In function 'intel_ddi_hdmi_level': drivers/gpu/drm/i915/intel_ddi.c:654:6: error: 'n_hdmi_entries' may be used uninitialized in this function [-Werror=maybe-uninitialized] It seems that the new cnl specific get_buf_trans functions can return uninitialized data if the voltage level is set to an unexpected value. This changes the code to always return '1' in that error case, which seems like the safest choice as we use one less than the number as an array index later on. Fixes: cc9cabfdec38 ("drm/i915/cnl: Move voltage check into ddi buf trans functions.") Signed-off-by: Arnd Bergmann <arnd@arndb.de> [danvet: shut up gcc comment added.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20171005120835.437022-1-arnd@arndb.de
* drm/i915/mst: Use MST sideband message transactions for dpms controlDhinakaran Pandiyan2017-10-051-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions to set power states for downstream sinks. Apart from giving us the ability to set power state for individual sinks, this fixes the below test for me. $ xrandr --display :0 --output DP-2-2-8 --off $ xrandr --display :0 --output DP-2-2-1 --off $ xrandr --display :0 --output DP-2-2-8 --auto #Black screen $ xrandr --display :0 --output DP-2-2-1 --auto v2: Modify and document the dpms and port disable order (Ville) Add comment explaining is_mst = !crtc_state equivalence(Ville, Maarten) v3 by Jani: rebase References: https://bugs.freedesktop.org/show_bug.cgi?id=90963 References: https://bugs.freedesktop.org/show_bug.cgi?id=88124 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lyude <lyude@redhat.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003142211.860-1-jani.nikula@intel.com
* drm/i915: Fix DDI PHY init if it was already onImre Deak2017-10-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The common lane power down flag of a DPIO PHY has a funky semantic: after the initial enabling of the PHY (so from a disabled state) this flag will be clear. It will be set only after the PHY will be used for the first time (for instance due to enabling the corresponding pipe) and then become unused (due to disabling the pipe). During the initial PHY enablement we don't know which of the above phases we are in, so move the check for the flag where this is known, the HW readout code. This is where the rest of lane power down status checks are done anyway. This fixes at least a problem on GLK where after module reloading, the common lane power down flag of PHY1 is set, but the PHY is actually powered-on and properly set up. The GRC readout code for other PHYs will hence think that PHY1 is not powered initially and disable it after the GRC readout. This will cause the AUX power well related to PHY1 to get disabled in a stuck state, timing out when we try to enable it later. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Fixes: e93da0a0137b ("drm/i915/bxt: Sanitiy check the PHY lane power down status") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102777 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171002135307.26117-1-imre.deak@intel.com
* drm/i915: Shrink cnl_ddi_buf_transVille Syrjälä2017-09-191-5/+5
| | | | | | | | | | All the values we put into the CNL buf_trans tables fit into 8 bits. So switch over to u8 from the u32 we use currently. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170918182604.9519-4-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Shrink bxt_ddi_buf_transVille Syrjälä2017-09-191-4/+4
| | | | | | | | | | All the values we put into the BXT buf_trans tables fit into 8 bits. So switch over to u8 from the u32 we use currently. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170918182604.9519-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Replace some spaces with tabsVille Syrjälä2017-09-191-3/+3
| | | | | | | | | | Some comments in intel_ddi.c are indented with spaces instead of tabs. Fix that up. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170918182604.9519-2-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACTION_SHIFTManasi Navare2017-09-141-1/+1
| | | | | | | | | | | | | No functional changes. Only change the macro from "DPLL_CFGCR0_DC0_FRAC_SHIFT to DPLL_CFGCR0_DCO_FRACTION_SHIFT to be consistent with DPLL_CFGCR0_DCO_FRACTION_MASK and DPLL_CFGCR0_DCO_FRACTION Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1505413899-30876-1-git-send-email-manasi.d.navare@intel.com
* drm/i915/cnl: Fix DP max voltageRodrigo Vivi2017-08-311-4/+11
| | | | | | | | | | | | | | | | | | | | On clock recovery this function is called to find out the max voltage swing level that we could go. However gen 9 functions use the old buffer translation tables to figure that out. That table is not valid for CNL causing an invalid number of entries and an invalid selection on the max voltage swing level. v2: Let's use same approach that previous platforms. v3: Actually use n_entries and avoid duplicated -1. v4: Avoid cnl_max_level and use current style. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170831145356.15932-1-rodrigo.vivi@intel.com
* drm/i915/cnl: Fix DDI hdmi level selection.Rodrigo Vivi2017-08-311-1/+4
| | | | | | | | | | | | Let's get a proper HDMI DDI entry level for vswing programming sequences on CNL. Spec doesn't specify any default for HDMI tables, so let's pick the last entry as the default for now. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-7-rodrigo.vivi@intel.com
* drm/i915/cnl: Move ddi buf trans related functions up.Rodrigo Vivi2017-08-311-61/+61
| | | | | | | | | | | No functional changes. But those functions will be needed to get max level for HDMI and DP, so let's move those up closer to other similar functions existent for previous platforms. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-6-rodrigo.vivi@intel.com
* drm/i915/cnl: Move voltage check into ddi buf trans functions.Rodrigo Vivi2017-08-311-27/+21
| | | | | | | | | | | | Let's start converging CNL buf translations to same style used on previous platforms. So first thing is to use the standard signature so we don't need to propagate the voltage check into other parts of the code, but only on the parts that it is really useful. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-5-rodrigo.vivi@intel.com
* drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.Rodrigo Vivi2017-08-311-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sequences for DisplayPort asks us to " Configure voltage swing and related IO settings. Refer to DDI Buffer section." before "Configure and enable DDI_BUF_CTL" On BXT and CNL this means to execute the ddi vswing sequences. At this point these sequences calls are getting duplicated for DP because they are all called from DP link trainning sequences. However this patch is not yet removing it before a futher discussion since spec also allows that during link training without disabling anything: " Notes Changing voltage swing during link training: Change the swing setting following the DDI Buffer section. The port does not need to be disabled. " Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-4-rodrigo.vivi@intel.com
* drm/i915: Align vswing sequences with old ddi buffer registers.Rodrigo Vivi2017-08-311-12/+10
| | | | | | | | | | | | | | | | | | | | Vswing sequences on BXT and CNL are equivalent to the ddi buffer registers setting on other platforms. For some reason it got aligned with skl_ddi_set_iboost what is semantically incorrect. This forced us to keep skipping ddi buffer translation tables on the platforms that has the vswing sequences. v2: Don't mess with DP signal levels on this patch. Cc: Vandana Kannan <vandana.kannan@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-3-rodrigo.vivi@intel.com
* drm/i915: decouple gen9 and gen10 dp signal levels.Rodrigo Vivi2017-08-311-9/+18
| | | | | | | | | | | | | | | | | | Let's decouple bxt, glk and cnl dp signal levels from other DDIs to avoid confusion. No functional change. Only a reorg to avoid messing with currently working DP signal levels when moving voltage swing sequences around to match spec. v2: ddi_signal_levels is also called from other ddi platforms, so don't remove IS_GEN9_BC check from skl_ddi_set_iboos. (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-2-rodrigo.vivi@intel.com
* drm/i915: Introduce intel_ddi_dp_level.Rodrigo Vivi2017-08-311-6/+10
| | | | | | | | | | | No functional changes. This only moves the DP level selection to a separated function that will be later used to organize better the vswing sequences. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-1-rodrigo.vivi@intel.com
* drm/i915: Constify states passed to enable/disable/etc. encoder hooksVille Syrjälä2017-08-221-15/+15
| | | | | | | | | | | | | | The enable/disable/etc. encoder hooks aren't supposed to alter the state(s), so pass them as const. Unfortunately C lacks any kind of deep const thingy, so this can't catch all abuses. But at least it acts as a hint to the reader telling them not to mess about with the state(s). v2: Update intel_tv_mode_find() and ironlake_edp_pll_on() as well v3: Deal with intel_sdvo_connector_state Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170818134958.15502-9-ville.syrjala@linux.intel.com
* drm/i915: Plumb crtc_state to PSR enable/disableVille Syrjälä2017-08-221-2/+2
| | | | | | | | | | | | | The PSR enable/disable need to know things about the crtc state, so plumb it through. This will become even more important when we start to reuse the generic infoframe code for the VSC DIP programming as the infoframe code wants the crtc state as well. v2: Fix kernel docs Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170818134958.15502-7-ville.syrjala@linux.intel.com
* drm/i915: Init infoframe vfuncs for DP encoders as wellVille Syrjälä2017-08-221-0/+2
| | | | | | | | | | DP ports may want to use the video DIP for SDP transmission, so let's initialize the vfuncs for DP encoders as well. The only exception is port A eDP prior to HSW as that one doesn't have a video DIP instance. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170818134958.15502-6-ville.syrjala@linux.intel.com
* drm/i915: Move infoframe vfuncs into intel_digital_portVille Syrjälä2017-08-221-12/+10
| | | | | | | | | | | DP ports will also want to utilize the video DIP for SDP transmission. So let's move the vfuncs into the dig_port. v2: Rebase due to DDI changes Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170818134958.15502-5-ville.syrjala@linux.intel.com
* drm/i915: Disable infoframes when shutting down DDI HDMIVille Syrjälä2017-08-221-3/+12
| | | | | | | | | | | | | | | | | | | | | | Disabling the video DIP when shutting the port down seems like a good idea. Bspec says: "When disabling both the DIP port and DIP transmission, first disable the port and then disable DIP." and "Restriction : GCP is only supported with HDMI when the bits per color is not equal to 8. GCP must be enabled prior to enabling TRANS_DDI_FUNC_CTL for HDMI with bits per color not equal to 8 and disabled after disabling TRANS_DDI_FUNC_CTL" So let's do it in the .post_disable() hook. v2: Remove double "dpms off" caused by rebase fail Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170822140914.24413-1-ville.syrjala@linux.intel.com
* drm/i915: Check has_infoframes when enabling infoframesVille Syrjälä2017-08-221-3/+3
| | | | | | | | | has_infoframe is what tells us whether infoframes should be enabled, so let's pass that instead of has_hdmi_sink to .set_infoframes(). Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170818134958.15502-3-ville.syrjala@linux.intel.com
* drm/i915: Return correct EDP voltage swing table for 0.85VMatthias Kaehlcke2017-08-111-1/+1
| | | | | | | | | | | | | | | | | | For 0.85V cnl_get_buf_trans_edp() returns the DP table, instead of EDP. Use the correct table. The error was pointed out by this clang warning: drivers/gpu/drm/i915/intel_ddi.c:392:39: warning: variable 'cnl_ddi_translations_edp_0_85V' is not needed and will not be emitted [-Wunneeded-internal-declaration] static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170717195854.192139-1-mka@chromium.org
* drm/i915/cnl: Fix loadgen select programming on ddi vswing sequenceNavare, Manasi D2017-07-271-2/+2
| | | | | | | | | | | | | | | | | The condition for setting the Loadgen Select bit of PORT_TX_DW4 register during DDI Vswing Sequence should be Bit rate <=6 GHz whereas the existing code checks only Bit Rate < 6GHz. This patch fixes this condition. While at it also remove the redundant paranthesis. Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1500329122-32662-1-git-send-email-manasi.d.navare@intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: prepare pipe for YCBCR420 outputShashank Sharma2017-07-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get HDMI YCBCR420 output, the PIPEMISC register should be programmed to: - Generate YCBCR output (bit 11) - In case of YCBCR420 outputs, it should be programmed in full blend mode to use the scaler in 5x3 ratio (bits 26 and 27) This patch: - Adds definition of these bits. - Programs PIPEMISC for YCBCR420 outputs. - Adds readouts to compare HW and SW states. V2: rebase V3: rebase V4: rebase V5: added r-b from Ander V6: Handle only YCBCR420 outputs (ville) V7: rebase V8: Addressed review comments from Ville - Add readouts for state->ycbcr420 and 420 pixel_clock. - Handle warning due to mismatch in clock for ycbcr420 clock. - Rename PIPEMISC macros to match the Bspec. - Add a debug print stating if YCBCR 4:2:0 output enabled. Added r-b from Ville V9: Addressed review comments from Imre: - Add 420 mode clock adjustment in intel_hdmi_mode_valid to prevent 420_only modes getting rejected for high clock. - Add port clock adjustment for ycbcr420 modes in ddi_get_clock - Rename macros as per Ville's suggestion. - Remove unnecessary wl changes. V10: Added r-b from Imre V11: Fixed faulty dotclock handling, and addressed missing comment from previous set of review comments (Imre) V12: Fixed dotclock for 12bpc too, removed 420 check for GEN < 10 Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1500904172-31717-1-git-send-email-shashank.sharma@intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/cnl: Add missing type case.Rodrigo Vivi2017-07-111-1/+4
| | | | | | | | | | | | | | | | | | | | Paulo had noticed that inside cnl_ddi_vswing_program the case was handling voltage but with no indication of type where a missing type could also take us to that path. So my first attempt was to add a message to let clear who trigger that path. However DK had a better idea that is to handle the missed type sooner before it might take to that path. So this v2 here uses his approach. v2: Handle missed type sooner. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170710205852.28352-1-rodrigo.vivi@intel.com
* drm/i915/cnl: Get DDI clock based on PLLs.Rodrigo Vivi2017-07-071-0/+111
| | | | | | | | | | | | | | PLLs are the source clocks for the DDIs so in order to determine the ddi clock we need to check the PLL configuration. v2: Mika pointed out that 24 was hardcoded while it should consider ref clock that can be either 24KHz or 19.2KHz on CNL. Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1499374321-31152-1-git-send-email-rodrigo.vivi@intel.com
* drm/i915/cnl: Fix RMW on ddi vswing sequence.Rodrigo Vivi2017-06-191-0/+7
| | | | | | | | | | | | | | | | | Paulo noticed that we were missing few bits clear before writing values back to the register on these RMW MMIO operations. v2: Remove "POST_" from CURSOR_COEFF_MASK. (Paulo). v3: Remove unnecessary braces. (Jani). Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com
* drm/i915/cfl: Basic DDI plumbing for Coffee Lake.Rodrigo Vivi2017-06-121-6/+7
| | | | | | | | | | | | | | | | | | | | | All here is pretty much like Kabylake. Including CFL-U has to use same ddi translation table as KBL-U for now. v2: Include missed IS_COFFEELAKE on edp trans table. (DK) Handle CFL-U with same translation table as KBL-U. (DK and confirmed with HW engineers) v3: Adding missed case for IS_CFL_ULT. (DK). v4: Duh! Now with the real IS_CFL_ULT instead of KBL one. (DK) Also use IS_GEN9_BC when possible. (DK) Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1497045770-21302-1-git-send-email-rodrigo.vivi@intel.com
* drm/i915/cnl: Enable loadgen_select bit for vswing sequenceClint Taylor2017-06-121-6/+32
| | | | | | | | | | | | | | vswing programming sequence step 2 requires the Loadgen_select bit to be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and lane width. Implemented the change that was marked as FIXME in the driver. v2: (Rodrigo) checkpatch fixes. Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-12-git-send-email-rodrigo.vivi@intel.com
OpenPOWER on IntegriCloud