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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915: interrupt & vblank support for Ivy BridgeJesse Barnes2011-05-131-0/+13
| | | | | | | | Add new interrupt handling functions for Ivy Bridge. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: manual FDI training for Ivy BridgeJesse Barnes2011-05-131-0/+10
| | | | | | | | | A0 stepping chips need to use manual training, but the bits have all moved. So fix things up so we can at least train FDI for VGA links. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
* drm/i915: move gen6 rps handling to workqueueBen Widawsky2011-05-101-1/+4
| | | | | | | | | | | | The render P-state handling code requires reading from a GT register. This means that FORCEWAKE must be written to, a resource which is shared and should be protected by struct_mutex. Hence we can not manipulate that register from within the interrupt handling and so must delegate the task to a workqueue. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
* Merge commit '5359533801e3dd3abca5b7d3d985b0b33fd9fe8b' into drm-core-nextDave Airlie2011-03-161-0/+10
|\ | | | | | | | | | | | | | | | | | | This commit changed an internal radeon structure, that meant a new driver in -next had to be fixed up, merge in the commit and fix up the driver. Also fixes a trivial nouveau merge. Conflicts: drivers/gpu/drm/nouveau/nouveau_mem.c
| * drm/i915: Revive combination mode for backlight controlTakashi Iwai2011-03-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 951f3512dba5bd44cda3e5ee22b4b522e4bb09fb drm/i915: Do not handle backlight combination mode specially since this commit introduced other regressions due to untouched LBPC register, e.g. the backlight dimmed after resume. In addition to the revert, this patch includes a fix for the original issue (weird backlight levels) by removing the wrong bit shift for computing the current backlight level. Also, including typo fixes (lpbc -> lbpc). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34524 Acked-by: Indan Zupancic <indan@nul.nu> Reviewed-by: Keith Packard <keithp@keithp.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: <stable@kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2011-03-071-0/+2
|\ \ | |/ | | | | | | | | | | | | | | Apply the trivial conflicting regression fixes, but keep GPU semaphores enabled. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_execbuffer.c
| * drm/i915: Do not overflow the MMADDR write FIFOChris Wilson2011-03-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whilst the GT is powered down (rc6), writes to MMADDR are placed in a FIFO by the System Agent. This is a limited resource, only 64 entries, of which 20 are reserved for Display and PCH writes, and so we must take care not to queue up too many writes. To avoid this, there is counter which we can poll to ensure there are sufficient free entries in the fifo. "Issuing a write to a full FIFO is not supported; at worst it could result in corruption or a system hang." Reported-and-Tested-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"Chris Wilson2011-03-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I stumbled over this magic bit in the gen3 INSTPM: Bit11 Interrupt-Based AGPBUSY# Enable: ‘0’ = Pending GMCH interrupts will not cause AGPBUSY# assertion. ‘1’ = Pending GMCH interrupts will cause AGPBUSY# assertion and hence can cause the CPU to exit C3. There is no suppression of cacheable writes. Note that in either case in C3 the interrupts are not lost. They will be forwarded to the ICH when the GMCH is out of C3. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@kernel.org
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2011-02-221-10/+0
|\ \ | |/ | | | | | | | | | | | | | | | | Merge in the conflicting eDP fix. Conflicts: drivers/gpu/drm/i915/i915_irq.c drivers/gpu/drm/i915/intel_display.c Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Do not handle backlight combination mode speciallyIndan Zupancic2011-02-211-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code does not follow Intel documentation: It misses some things and does other, undocumented things. This causes wrong backlight values in certain conditions. Instead of adding tricky code handling badly documented and rare corner cases, don't handle combination mode specially at all. This way PCI_LBPC is never touched and weird things shouldn't happen. If combination mode is enabled, then the only downside is that changing the brightness has a greater granularity (the LBPC value), but LBPC is at most 254 and the maximum is in the thousands, so this is no real functional loss. A potential problem with not handling combined mode is that a brightness of max * PCI_LBPC is not bright enough. However, this is very unlikely because from the documentation LBPC seems to act as a scaling factor and doesn't look like it's supposed to be changed after boot. The value at boot should always result in a bright enough screen. IMPORTANT: However, although usually the above is true, it may not be when people ran an older (2.6.37) kernel which messed up the LBPC register, and they are unlucky enough to have a BIOS that saves and restores the LBPC value. Then a good kernel may seem to not work: Max brightness isn't bright enough. If this happens people should boot back into the old kernel, set brightness to the maximum, and then reboot. After that everything should be fine. For more information see the below links. This fixes bugs: http://bugzilla.kernel.org/show_bug.cgi?id=23472 http://bugzilla.kernel.org/show_bug.cgi?id=25072 Signed-off-by: Indan Zupancic <indan@nul.nu> Tested-by: Alex Riesen <raa.lkml@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | drm/i915: Add support for limited color range of broadcast outputsChris Wilson2011-02-221-0/+1
| | | | | | | | | | | | | | | | | | In order to prevent "crushed blacks" on TVs, the range of the RGB output may be limited to 16-235. This used to be available through Xorg under the "Broadcast RGB" option, so reintroduce support for KMS. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34543 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2011-02-161-1/+3
|\ \ | |/ | | | | | | | | | | | | | | Grab the latest stabilisation bits from -fixes and some suspend and resume fixes from linus. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_irq.c
| * drm/i915: Invalidate TLB caches on SNB BLT/BSD ringsChris Wilson2011-02-021-1/+3
| | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
* | drm/i915: disable PCH ports if needed when disabling a CRTCJesse Barnes2011-02-111-0/+15
| | | | | | | | | | | | | | | | | | Disable any PCH ports associated with a pipe when disabling it. This should prevent transcoder disable failures due to ports still being on. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: introduce *_PIPE_ENABLED() macro] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: cleanup per-pipe reg usageJesse Barnes2011-02-071-201/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | We had some conversions over to the _PIPE macros, but didn't get everything. So hide the per-pipe regs with an _ (still used in a few places for legacy) and add a few _PIPE based macros, then make sure everyone uses them. [update: remove usage of non-existent no-op macro] [update 2: keep modesetting suspend/resume code, update to new reg names] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: stylistic cleanups for checkpatch and taste] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Set the transcoder port to none when disabling DP.Eric Anholt2011-02-071-0/+1
| | | | | | | | | | | | | | The specs say to do so. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2011-01-201-0/+6
|\ \ | |/ | | | | Apply the SandyBridge stability fixes from -fixes.
| * drm/i915: make the blitter report buffer modifications to the FBC unitJesse Barnes2011-01-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | Without this change, blits to the front buffer won't invalidate FBC state, causing us to scan out stale data. Make sure we update these bits on every FBC enable, since they may get clobbered if we shut off the display. References: https://bugzilla.kernel.org/show_bug.cgi?id=26932 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: set more FBC chicken bitsJesse Barnes2011-01-181-0/+2
| | | | | | | | | | | | | | | | | | Add a couple of missing workaround bits for ILK & SNB. These disable clock gating on a couple of units that would otherwise prevent FBC from working. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Honour LVDS sync polarity from EDIDBryan Freed2011-01-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The i915 driver normally assumes the video bios has configured several of the LVDS panel registers, and it just inherits the values. If the vbios has not run, several of these will need to be setup. So we need to check that the LVDS sync polarity is correctly configured per any available modelines (e.g. EDID) and adjust if not, issuing a warning as we do. Signed-off-by: Mark Hayter <mdhayter@chromium.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: tune Sandy Bridge DRPS constantsJesse Barnes2011-01-191-2/+15
| | | | | | | | | | | | | | | | | | These make us increase our frequency much more readily, and decrease them only after significant idle time, resulting in a 20% performance increase for nexuiz. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: set phase sync pointer override enable before setting phase sync ↵Jesse Barnes2011-01-191-1/+2
| | | | | | | | | | | | | | | | | | | | pointer We need to unlock the phase sync pointer enable bit before we can actually enable the phase sync pointer workaround on Ironlake. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: add PCH DPLL enable/disable functionsJesse Barnes2011-01-191-0/+1
| | | | | | | | | | | | | | With assertions to check transcoder and reference clock state. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: add pipe/plane enable/disable functionsJesse Barnes2011-01-191-2/+3
|/ | | | | | | | | Add plane enable/disable functions to prevent duplicated code and allow us to easily check for plane enable/disable requirements (such as pipe enable, plane status, pll status etc). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: detect & report PCH display error interruptsJesse Barnes2011-01-111-0/+29
| | | | | | | | FDI and the transcoders can fail for various reasons, so detect those conditions and report on them. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes2011-01-111-3/+47
| | | | | | | | | | | | | Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Mask USER interrupts on gen6 (until required)Chris Wilson2011-01-111-0/+1
| | | | | | | Otherwise we may consume 20% of the CPU just handling IRQs whilst rendering. Ouch. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: support low power watermarks on IronlakeJesse Barnes2011-01-111-0/+5
| | | | | | | | | | | | | | | This patch actually makes the watermark code even uglier (if that's possible), but has the advantage of sharing code between SNB and ILK at least. Longer term we should refactor the watermark stuff into its own file and clean it up now that we know how it's supposed to work. Supporting WM2 on my Vaio reduced power consumption by around 0.5W, so this patch is definitely worthwhile (though it also needs lots of test coverage). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: pass the watermark structs arounds] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: support overclocking on Sandy BridgeJesse Barnes2011-01-111-0/+1
| | | | | | | | | | In some configuration, the PCU may allow us to overclock the GPU. Check for this case and adjust the max frequency as appropriate. Also initialize the min/max frequencies to default values as indicated by hardware. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: fix calculation of eDP signal levels on SandybridgeYuanhan Liu2011-01-111-4/+5
| | | | | | | | | | | Some voltage swing/pre-emphasis level use the same value on eDP Sandybridge, like 400mv_0db and 600mv_0db are with the same value of (0x0 << 22). So, fix them, and point out the value if it isn't a supported voltage swing/pre-emphasis level. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
* Merge branch 'master' of /home/airlied/kernel/linux-2.6 into drm-core-nextDave Airlie2011-01-051-0/+10
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| * drm/i915: Verify Ironlake eDP presence on DP_A using the capability fuseChris Wilson2010-12-231-0/+7
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Set the required VFMUNIT clock gating disable on Ironlake.Eric Anholt2010-12-231-0/+3
| | | | | | | | | | | | | | | | It's required by the specs, but we don't know why. Let's not find out why. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes2010-12-181-1/+7
| | | | | | | | | | | | | | | | | | Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Add support for precise vblank timestamping (v2)Mario Kleiner2010-12-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37 This patch adds new functions for use by the drm core: .get_vblank_timestamp() provides a precise timestamp for the end of the most recent (or current) vblank interval of a given crtc, as needed for the DRI2 implementation of the OML_sync_control extension. It is a thin wrapper around the drm function drm_calc_vbltimestamp_from_scanoutpos() which does almost all the work. .get_scanout_position() provides the current horizontal and vertical video scanout position and "in vblank" status of a given crtc, as needed by the drm for use by drm_calc_vbltimestamp_from_scanoutpos(). The patch modifies the pageflip completion routine to use these precise vblank timestamps as the timestamps for pageflip completion events. This code has been only tested on a HP-Mini Netbook with Atom processor and Intel 945GME gpu. The codepath for (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's has not been tested so far due to lack of hardware. Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Add frame buffer compression on SandybridgeYuanhan Liu2010-12-151-0/+10
| | | | | | | | | | | | | | | | | | Add frame buffer compression on Sandybridge. The method is similar to Ironlake, except that two new registers of type GTTMMADR must be written with the right fence info. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Add self-refresh support on SandybridgeYuanhan Liu2010-12-151-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support of memory self-refresh on Sandybridge, which is now support 3 levels of watermarks and the source of the latency values for watermarks has changed. On Sandybridge, the LP0 WM value is not hardcoded any more. All the latency value is now should be extracted from MCHBAR SSKPD register. And the MCHBAR base address is changed, too. For the WM values, if any calculated watermark values is larger than the maximum value that can be programmed into the associated watermark register, that watermark must be disabled. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> [ickle: remove duplicate compute routines and fixup for checkpatch] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Enable RC6 autodownclocking on SandybridgeChris Wilson2010-12-091-0/+59
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Terminate the FORCE WAKE after we have finished readingChris Wilson2010-12-091-0/+1
| | | | | | | | | | | | | | Once we have read the value out of the GT power well, we need to remove the FORCE WAKE bit to allow the system to auto-power down. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBChris Wilson2010-12-051-1/+18
| | | | | | | | | | | | | | | | The bulk of the change is to convert the growing list of rings into an array so that the relationship between the rings and the semaphore sync registers can be easily computed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Enable CB tuning of the Display PLLChris Wilson2010-12-051-0/+1
| | | | | | | | | | | | | | | | Magic numbers from the specs. This is supposed to allow the PLL some variance to improve jitter performance and VCO headroom across manufacturing and environmental variations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-021-0/+1
|\ \ | |/ | | | | | | Conflicts: drivers/gpu/drm/i915/intel_drv.h
| * drm/i915: Always set the DP transcoder config to 8BPC.Eric Anholt2010-12-021-0/+1
| | | | | | | | | | | | | | | | | | | | The pipe is always set to 8BPC, but here we were leaving whatever previous bits were set by the BIOS in place. Signed-off-by: Eric Anholt <eric@anholt.net> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
* | drm/i915: Add a mechanism for pipelining fence register updatesDaniel Vetter2010-11-251-1/+7
| | | | | | | | | | | | | | Not employed just yet... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Add support for GPU reset on gen6.Eric Anholt2010-11-221-0/+6
| | | | | | | | | | | | | | | | | | | | This has proven sufficient to recover from a hang of the GPU using the gem_bad_blit test while at the KMS console then starting X. When attempting the same during an X session, the timer doesn't appear to trigger. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Capture interesting display registers on errorChris Wilson2010-11-221-1/+5
| | | | | | | | | | | | | | When trying to diagnose mysterious errors on resume, capture the display register contents as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Remove the definitions for Primary Ring BufferChris Wilson2010-11-111-4/+6
| | | | | | | | | | | | | | | | | | | | We only ever used the PRB0, neglecting the secondary ring buffers, and now with the advent of multiple engines with separate ring buffers we need to excise the anachronisms from our code (and be explicit about which ring we mean where). This is doubly important in light of the FORCEWAKE required to read ring buffer registers on SandyBridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring registerZou Nan hai2010-11-111-0/+1
| | | | | | | | | | | | | | | | | | Before reading ring register, set FORCE_WAKE bit to prevent GT core power down to low power state, otherwise we may read stale values. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [ickle: added a udelay which seemed to do the trick on my SNB] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Apply display workaround required according to the B-Spec.Eric Anholt2010-11-081-0/+2
| | | | | | | | | | | | | | Not known to fix any current bugs. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.Eric Anholt2010-11-081-0/+13
| | | | | | | | | | | | | | | | This is not known to fix any particular bugs we have, but the spec says to do it, and the BIOS hadn't already set it up on my system. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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