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path: root/drivers/gpu/drm/i915/i915_debugfs.c
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* drm/i915: report correct render clock frequencies on SNBJesse Barnes2011-03-231-4/+4
| | | | | | | | | | | Fix up the debug file to report the right frequencies. On SNB, we program the PCU with a frequency ratio, which is multiplied by 100MHz on the CPU side. But GFX only runs at half that, so report it as such to avoid confusion. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Keith Packard <keithp@keithp.com>
* Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2011-03-071-2/+2
|\ | | | | | | | | | | | | | | | | Apply the trivial conflicting regression fixes, but keep GPU semaphores enabled. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_execbuffer.c
| * drm/i915: Do not overflow the MMADDR write FIFOChris Wilson2011-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whilst the GT is powered down (rc6), writes to MMADDR are placed in a FIFO by the System Agent. This is a limited resource, only 64 entries, of which 20 are reserved for Display and PCH writes, and so we must take care not to queue up too many writes. To avoid this, there is counter which we can poll to ensure there are sufficient free entries in the fifo. "Issuing a write to a full FIFO is not supported; at worst it could result in corruption or a system hang." Reported-and-Tested-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: cleanup per-pipe reg usageJesse Barnes2011-02-071-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | We had some conversions over to the _PIPE macros, but didn't get everything. So hide the per-pipe regs with an _ (still used in a few places for legacy) and add a few _PIPE based macros, then make sure everyone uses them. [update: remove usage of non-existent no-op macro] [update 2: keep modesetting suspend/resume code, update to new reg names] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: stylistic cleanups for checkpatch and taste] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Record all error ringbuffersChris Wilson2011-01-281-9/+14
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: tune Sandy Bridge DRPS constantsJesse Barnes2011-01-191-1/+26
| | | | | | | | | | | | | | | | | | These make us increase our frequency much more readily, and decrease them only after significant idle time, resulting in a 20% performance increase for nexuiz. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Trivial sparse fixesChris Wilson2011-01-191-4/+4
|/ | | | | | | Move code around and invoke iomem annotation in a few more places in order to silence sparse. Still a few more iomem annotations to go... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debugfs: Correct format after changing type of err object 'size'Chris Wilson2011-01-121-1/+1
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debugfs: Show all objects in the gttChris Wilson2011-01-111-10/+43
| | | | | | Useful for determining the layout. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Record AGP memory type upon errorChris Wilson2011-01-111-2/+12
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Record the error batchbuffer on each ringChris Wilson2011-01-111-1/+3
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes2011-01-111-1/+25
| | | | | | | | | | | | | Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debugfs: Show the per-ring IMRChris Wilson2011-01-111-1/+7
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes2010-12-181-9/+45
| | | | | | | | | Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Add self-refresh support on SandybridgeYuanhan Liu2010-12-151-1/+1
| | | | | | | | | | | | | | | | | | Add the support of memory self-refresh on Sandybridge, which is now support 3 levels of watermarks and the source of the latency values for watermarks has changed. On Sandybridge, the LP0 WM value is not hardcoded any more. All the latency value is now should be extracted from MCHBAR SSKPD register. And the MCHBAR base address is changed, too. For the WM values, if any calculated watermark values is larger than the maximum value that can be programmed into the associated watermark register, that watermark must be disabled. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> [ickle: remove duplicate compute routines and fixup for checkpatch] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: caps.has_rc6 is no longer used, remove it.Chris Wilson2010-12-051-1/+0
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBChris Wilson2010-12-051-45/+30
| | | | | | | | The bulk of the change is to convert the growing list of rings into an array so that the relationship between the rings and the semaphore sync registers can be easily computed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Defer accounting until read from debugfsChris Wilson2010-11-251-13/+71
| | | | | | | | | | Simply remove our accounting of objects inside the aperture, keeping only track of what is in the aperture and its current usage. This removes the over-complication of BUGs that were attempting to keep the accounting correct and also removes the overhead of the accounting on the hot-paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: More accurately track last fence usage by the GPUChris Wilson2010-11-241-1/+2
| | | | | | Based on a patch by Daniel Vetter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Record fence registers on error.Chris Wilson2010-11-231-0/+3
| | | | | | | | Having seen the effects of erroneous fencing on the batchbuffer, a useful sanity check is to record the fence registers at the time of an error. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Use drm_i915_gem_object as the preferred typeChris Wilson2010-11-231-34/+30
| | | | | | | A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and many characters! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Avoid oops when capturing NULL ring for inactive pinned buffersChris Wilson2010-11-231-3/+3
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Capture interesting display registers on errorChris Wilson2010-11-221-0/+3
| | | | | | | When trying to diagnose mysterious errors on resume, capture the display register contents as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Capture pinned buffers on errorChris Wilson2010-11-221-24/+39
| | | | | | | | The pinned buffers are useful for diagnosing errors in setting up state for the chipset, which may not necessarily be 'active' at the time of the error, e.g. the cursor buffer object. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Remove the global irq wait queueChris Wilson2010-11-111-7/+1
| | | | | | ... as it has been replaced by per-ring waiters. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debugfs: Report ring in error stateChris Wilson2010-11-011-28/+34
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Record BSD engine error stateChris Wilson2010-10-291-0/+6
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debugfs: Display the contents of the BLT and BSD status pagesChris Wilson2010-10-291-3/+13
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Record BLT engine error stateChris Wilson2010-10-291-6/+13
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only enforce fence limits inside the GTT.Chris Wilson2010-10-291-1/+2
| | | | | | | | | | | | | So long as we adhere to the fence registers rules for alignment and no overlaps (including with unfenced accesses to linear memory) and account for the tiled access in our size allocation, we do not have to allocate the full fenced region for the object. This allows us to fight the bloat tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside the GTT we still suffer the additional alignment constraints, so it doesn't magic allow us to render larger scenes without stalls -- we need the expanded GTT and fence pipelining to overcome those...] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Capture ERROR register on Sandybridge hangsChris Wilson2010-10-271-0/+3
| | | | | | | This holds error state from the main graphics arbiter mainly involving the DMA engine and address translation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: add accounting for mappable objects in gtt v2Daniel Vetter2010-10-271-0/+6
| | | | | | | | | | | | | | | More precisely: For those that _need_ to be mappable. Also add two BUG_ONs in fault and pin to check the consistency of the mappable flag. Changes in v2: - Add tracking of gtt mappable space (to notice mappable/unmappable balancing issues). - Improve the mappable working set tracking by tracking fault and pin separately. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Remove the confusing global waiting/irq seqnoChris Wilson2010-10-271-25/+19
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/debugfs: Include info for the other ringsChris Wilson2010-10-271-41/+93
| | | | | | | The render ring is not alone any more! And the other rings are just as troublesome... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Drop the redundant dev from the vfunc interfaceChris Wilson2010-10-271-2/+2
| | | | | | | The ringbuffer keeps a pointer to the parent device, so we can use that instead of passing around the pointer on the stack. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* Merge branch 'drm-core-next' of ↵Linus Torvalds2010-10-261-69/+267
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits) vmwgfx: Implement a proper GMR eviction mechanism drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2 drm/radeon/kms: properly compute group_size on 6xx/7xx drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker drm/radeon/kms/evergreen: set the clear state to the blit state drm/radeon/kms: don't poll dac load detect. gpu: Add Intel GMA500(Poulsbo) Stub Driver drm/radeon/kms: MC vram map needs to be >= pci aperture size drm/radeon/kms: implement display watermark support for evergreen drm/radeon/kms/evergreen: add some additional safe regs v2 drm/radeon/r600: fix tiling issues in CS checker. drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 ... Fix up conflicts in - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the new simplified stack-based kmap_atomic() interface - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL removal cleanups.
| * drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson2010-10-211-2/+1
| | | | | | | | | | | | | | So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Enable SandyBridge blitter ringChris Wilson2010-10-211-0/+2
| | | | | | | | | | | | | | | | Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Track objects in global active list (as well as per-ring)Chris Wilson2010-10-201-14/+9
| | | | | | | | | | | | | | | | | | | | | | To handle retirements, we need per-ring tracking of active objects. To handle evictions, we need global tracking of active objects. As we enable more rings, rebuilding the global list from the individual per-ring lists quickly grows tiresome and overly complicated. Tracking the active objects in two lists is the lesser of two evils. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm: Move the GTT accounting to i915Chris Wilson2010-10-011-0/+26
| | | | | | | | | | | | | | | | | | Only drm/i915 does the bookkeeping that makes the information useful, and the information maintained is driver specific, so move it out of the core and into its single user. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Airlie <airlied@redhat.com>
| * drm/i915: Make get/put pages staticChris Wilson2010-09-301-15/+11
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915/debugfs: Include list totalsChris Wilson2010-09-301-2/+9
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Report the deferred free list in debugfsChris Wilson2010-09-301-1/+7
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Only hold a process-local lock whilst throttling.Chris Wilson2010-09-241-3/+3
| | | | | | | | | | | | | | | | | | Avoid cause latencies in other clients by not taking the global struct mutex and moving the per-client request manipulation a local per-client mutex. For example, this allows a compositor to schedule a page-flip (through X) whilst an OpenGL application is monopolising the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Track pinned objectsChris Wilson2010-09-211-4/+12
| | | | | | | | | | | | | | | | Keep a list of pinned objects and display it via debugfs. Now all objects that exist in the GTT are always tracked on one of the active, flushing, inactive or pinned lists. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915/debug: Dump BSD ring buffers to debugfsChris Wilson2010-09-211-6/+12
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson2010-09-211-7/+4
| | | | | | | | | | | | | | Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Fix updating FBCChris Wilson2010-09-111-0/+3
| | | | | | | | | | | | | | We need to track different state on each generation in order to detect when we need to refresh the FBC registers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915/debug: Include Ironlake in self-refresh statusChris Wilson2010-09-091-3/+5
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * i915: snprintf returns large valuesDan Carpenter2010-09-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | snprintf() returns the number of bytes which would have been used if there was enough space. It can be larger than the size of the buffer. Obviously in this case the buffer is large enough but everyone just copy and pastes this code so it's better to limit it and set a good example. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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