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| * | drm/amd/display: add method to check for supported rangeAnthony Koo2018-08-272-6/+65
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Refactor FreeSync moduleAnthony Koo2018-08-2714-1670/+930
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove dependency on internal sink map and instead use existing stream and plane state Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_moduleHarry Wentland2018-08-271-11/+29
| | | | | | | | | | | | | | | | | | | | | Add code to tear down freesync modules when disabled. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu:change VEGA booting with firmware loaded by PSPFeifei Xu2018-08-271-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With PSP firmware loading, TMR mc address is supposed to be used. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: added support 2nd UVD instanceEvan Quan2018-08-274-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added psp fw loading support for vega20 2nd UVD instance. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use entity instead of ring for CSChristian König2018-08-276-66/+78
| | | | | | | | | | | | | | | | | | | | | | | | Further demangle ring from entity handling. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: move context related stuff to amdgpu_ctx.hChristian König2018-08-272-57/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | Further unmangle amdgpu.h. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove ring lru handlingChristian König2018-08-272-103/+0
| | | | | | | | | | | | | | | | | | | | | | | | Not needed any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove the queue managerChristian König2018-08-275-360/+75
| | | | | | | | | | | | | | | | | | | | | | | | Not needed any more since that is now done by the scheduler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use scheduler load balancing for compute CSChristian König2018-08-271-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Start to use the scheduler load balancing for userspace compute command submissions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use scheduler load balancing for SDMA CSChristian König2018-08-271-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Start to use the scheduler load balancing for userspace SDMA command submissions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use new scheduler load balancing for VMsChristian König2018-08-278-40/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of the fixed round robin use let the scheduler balance the load of page table updates. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Change VCE booting with firmware loaded by PSPJames Zhu2018-08-271-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With PSP firmware loading, TMR mc address is supposed to be used. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix integer overflow test in amdgpu_bo_list_create()Dan Carpenter2018-08-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We accidentally left out the size of the amdgpu_bo_list struct. It could lead to memory corruption on 32 bit systems. You'd have to pick the absolute maximum and set "num_entries == 59652323" then size would wrap to 16 bytes. Fixes: 920990cb080a ("drm/amdgpu: allocate the bo_list array after the list") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Bas Nieuwenhuizen <basni@chromium.org> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/pp: OverDrive gfx domain voltage on TongaRex Zhu2018-08-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also ajust the gfx domain voltage on Tonga when user overdriver the voltage. For Tonga, Driver do not update user's setting to voltage table in smu, we only pick up a minimum value from voltage table that not less than the user's setting. v2: fix a typo Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Cancel the delay work when suspendRex Zhu2018-08-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cancel the delay work to avoid the corner case that ib test was not running when suspend Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove experimental flag for vega20Alex Deucher2018-08-271-6/+6
| | | | | | | | | | | | | | | | | | Now that PSP and SMU support is in place. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/psp: Enlarge PSP TMR SIZE from 3M to 4M.Feifei Xu2018-08-272-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Enlarge the PSP TMR SIZE to 4M for dual UVD fw front-door loading. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: update vega20 sdma golden settingsEvan Quan2018-08-271-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated vega20 SDMA0 and SDMA1 golden settings. Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx9: Update gfx9 golden settings.Feifei Xu2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the goldensettings for vega20. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: added voltage boot time calibrationEvan Quan2018-08-271-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Run AFLL BTC after upload pptable and before enabling all smu features. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: remove max DCEFCLK limitationEvan Quan2018-08-271-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The latest SMU fw removes the limitation that required UCLK >= DCEFCLK. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: allow slow switch only if NBPState enabledEvan Quan2018-08-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Otherwise there may be potential SMU performance issues. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitchEvan Quan2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The argument was set wrongly. Fast/slow switch was asked when there is actually a slow/fast switch needed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twiceEvan Quan2018-08-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For vega20, there are two UVD rings which share one powerplay instance. Under some case(two rings used parallel), the uvd dpm is disabled twice which causes the SMC hang. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: remove setting soc floor voltage before sending pptableEvan Quan2018-08-272-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | SOC voltage is not able to switch and forced to low 0.8V when running HEVC. Thus the test failed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: enable fclk ss by defaultEvan Quan2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Set fclk ss as enabled on default. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/vg20: Change the load type of vega20 to psp (v2)Likun Gao2018-08-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified the vega20 load type to psp now that psp support is implemented. v2: squash in fixes history (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Add psp 11.0 support for vega20. (v2)Feifei Xu2018-08-277-6/+614
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add psp 11.0 code for vega20 and enable it. PSP is the security processor for the GPU. It handles firmware loading and GPU resets among other things. v2: whitespace fix, enable support, adjust reg includes (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable vega20 powerplay supportEvan Quan2018-08-271-2/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: update vega20 clocks threshold settings on power state adjustEvan Quan2018-08-271-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | UVD, VCE and SOC clocks need to be taken into consideration. Also, the thresholds need be updated correspondingly when stable power state is selected. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: revise vega20 PPSMC_MSG_SetSoftMin/[Max]ByFreq settingsEvan Quan2018-08-271-13/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | UVD, VCE and Socclk also need to be taken into consideration when setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: new interfaces for overdrive vega20 sclk and mclkEvan Quan2018-08-271-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the new SMU firmware interface for clock adjustment. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: initialize vega20 overdrive settingsEvan Quan2018-08-275-49/+403
| | | | | | | | | | | | | | | | | | | | | | | | | | | The initialized overdrive settings are taken from vbios and SMU( by PPSMC_MSG_TransferTableSmu2Dram). Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: conv the vega20 pstate sclk/mclk into necessary 10KHz unitEvan Quan2018-08-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Powerplay uses 10KHz units. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: add vega20 pre_display_config_changed callbackEvan Quan2018-08-271-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix possible handshake hang and video playback crash Corner cases: - Handshake between SMU and DCE causes hangs when CRTC is not enabled - System crash occurs when starting 4K playback with Movies and TV in an SLS configuration Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: export vega20 stable pstate clocksEvan Quan2018-08-271-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | Needed for querying the stable pstate clocks. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: correct force clock level related settings for vega20 (v2)Evan Quan2018-08-271-45/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. The min/max level is determined by soft_min_level/soft_max_level. 2. Vega20 comes with pptable v3 which has no vdd related table(vdd_dep_on_socclk, vdd_dep_on_mclk) support. 3. Vega20 does not support separate fan feature control(enable or disable). v2: squash in fixes: - bug fix for force dpm level settings - fix wrong data type Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setupEvan Quan2018-08-271-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | This is essentially necessary when uvd/vce dpm is not enabled yet. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: support workload profile query and setup for vega20Evan Quan2018-08-271-1/+192
| | | | | | | | | | | | | | | | | | | | | | | | Support the power profile API. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: add the hw manager for vega20 (v3)Evan Quan2018-08-2710-2/+3956
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hwmgr is the interface for the driver to setup state structures which are used by the smu for managing the power state. v2: squash in fixes: - update set_watermarks_for_clocks_ranges to use common code - drop unsupported apis - correct MAX_REGULAR_DPM_NUMBER value - multimonitor fixes - add check for vbios pptable version - revise dpm table setup - init fclk dpm state - Remove unused definition in vega20_hwmgr - support power limit setup - enable vega20 to honour DAL clock limits - comment out dump_table debugging v3: switch to SOC15 register access macros Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: new interfaces for ActivityMonitor table with SMUEvan Quan2018-08-272-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | Vega20 has a new activity monitor table that is stored in memory. Add API to get and set the new table. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: add the smu manager for vega20 (v2)Evan Quan2018-08-273-1/+592
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SMU manager handles the driver interaction with the SMU which handles clock and voltage controls. v2: switch to SOC15 register access macros reserve space for ActivityMonitor table enable SMU fw loading Drop dead code from bringup Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: add vega20_pptable.h (v2)Evan Quan2018-08-271-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | v2: squash in table size fixes Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: add vega20_ppsmc.h (v2)Evan Quan2018-08-271-0/+127
| | | | | | | | | | | | | | | | | | | | | | | | v2: update to latest. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: add smu11_driver_if.h (v4)Evan Quan2018-08-271-0/+831
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: cleanup v3: fit the latest 40.6 smc fw v4: update to latest. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: add vega20_inc.h (v2)Evan Quan2018-08-271-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | v2: use thm 11.0.2 headers Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: update atomfirmware.hEvan Quan2018-08-271-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | Add struct atom_smc_dpm_info_v4_3 Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Add nbio 7.4 support for vega20 (v3)Feifei Xu2018-08-275-1/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20. v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | Revert "drm/amdgpu: Add nbio support for vega20 (v2)"Alex Deucher2018-08-272-19/+1
| | | | | | | | | | | | | | | | | | | | | | | | Revert this to add proper nbio 7.4 support. This reverts commit f5b2e1fa321eff20a9418ebd497d8a466f024a85. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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